News Column

Patent Issued for Integrated Circuits Based on Aligned Nanotubes

July 29, 2014



By a News Reporter-Staff News Editor at Life Science Weekly -- From Alexandria, Virginia, NewsRx journalists report that a patent by the inventors Zhou, Chongwu (San Marino, CA); Ryu, Koungmin (Los Angeles, CA); Badmaev, Alexander (Hillsboro, OR); Wang, Chuan (Albany, CA), filed on January 14, 2013, was published online on July 15, 2014 (see also University of Southern California).

The patent's assignee for patent number 8778716 is University of Southern California (Los Angeles, CA).

News editors obtained the following quote from the background information supplied by the inventors: "This application relates to aligned nanotubes.

"Single-walled carbon nanotubes (SWNTs) may provide much better performance for electronics than traditional silicon due to their high carrier mobility and current-carrying capacity. Nanotubes can work as ballistic and high mobility transistors, and integrated logic circuits such as inverters and ring-oscillators can be constructed using individual nanotubes.

"Randomly grown nanotube networks can be used for flexible devices and circuits. However, the stripe-patterning used to remove heterogeneous percolative transport through metallic nanotube networks cannot be easily scaled to submicron regime, and only PMOS transistors have been demonstrated for the reported circuits."

As a supplement to the background information on this patent, NewsRx correspondents also obtained the inventors' summary information for this patent: "This application discloses techniques, apparatus and systems for full wafer-scale processing of massively aligned carbon nanotube arrays for high-performance submicron channel transistors and integrated nanotube circuits.

"In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate (1210); transferring the grown aligned nanotubes onto a target substrate (1220); and fabricating at least one device based on the transferred nanotubes (1230).

"Implementations can optionally include one or more of the following features. The at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate can be sized to be at least one of two inches in diameter. Growing the aligned nanotubes on the at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate can be carried out with a temperature ramping rate of less than one .degree. C. per minute but greater than zero .degree. C. per minute near a quartz phase transition temperature to avoid breakage of quartz wafer.

"Transferring the grown aligned nanotubes onto a target substrate can include coating the aligned nanotubes with a film; peeling off the film together with aligned nanotubes using a thermal tape to obtain a composite of the nanotubes and the film; pressing the composite of the nanotubes and the film against the target substrate; removing the thermal tape by heating up the target substrate; and removing the film to leave the nanotubes on the target substrate.

"The method can include stacking multiple transfers of nanotubes to increase tube density. Stacking multiple transfers can include stacking multiple composites of the nanotubes and the film on top of each other and over the target substrate. The stacked composites can be etched together to form a network of the aligned nanotubes on the target substrate. The film can include at last one of a metal film or a polymer film. The metal film can include at least one of aluminum or copper. The polymer film can include Poly(methyl methacrylate) (PMMA).

"The fabricating can include fabricating submicron back-gated nanotube transistors on the transferred nanotubes with SiO.sub.2 as a gate dielectric and Si as a back-gate at a wafer-scale. The fabricating can include fabricating submicron top-gated nanotube transistors on the transferred nanotubes with high-.kappa. Al.sub.2O.sub.3 or HfO.sub.2 as a gate dielectric and a metal electrode as a top-gate at a wafer-scale. Additionally, stacking multiple transfers of nanotubes can be performed to increase tube density. The fabricating can include fabricating submicron individual back-gated nanotube transistors on the transferred nanotubes with high-.kappa. Al.sub.2O.sub.3 or HfO.sub.2 as a back-gate dielectric and a metal electrode as an individual back-gate.

"The method can include using a defect-tolerant circuit design for a nanotube based integrated circuit, wherein the defect-tolerant circuit design comprises etching away unwanted nanotubes and using same group of nanotubes for the at least one device. The individual back-gated nanotube transistors can facilitate a doping process. The method can include using at least one metal with low work functions as source and drain contacts to align the nanotubes for at least one of n-type nanotube transistors, PN junctions, or CMOS integrated circuits. The at least one metal with low work functions comprises Scandium (Sc), Yttrium (Y), Gadolinium (Gd), Dysprosium (Dy), Ytterbium (Yb), or Terbium (Tb). The fabricating can include fabricating multiple wafer-scale devices comprising at least one of back-gated transistors, top-gated transistors, CMOS inverters, CMOS NOR logic gates, CMOS NAND logic gates, or ring oscillators.

"In another aspect, the described techniques can be used to implement a device that includes at least one of the following devices fabricated at a wafer-scale: submicron back-gated nanotube transistors fabricated on aligned nanotubes with SiO2 as a gate dielectric and Si as a back-gate; submicron top-gated nanotube transistors on aligned nanotubes with high-.kappa. Al.sub.2O.sub.3 or HfO.sub.2 as a gate dielectric and a metal electrode as atop-gate at a wafer-scale; or submicron individual back-gated nanotube transistors on aligned nanotubes with high-.kappa. Al.sub.2O.sub.3 or HfO.sub.2 as a back-gate dielectric and a metal electrode as an individual back-gate. The apparatus can include at least one of CMOS inverters, CMOS NOR logic gates, CMOS NAND logic gates, or ring oscillators.

"In another aspect, the described techniques can be used to implement an apparatus that includes a wafer that includes at least one of the following devices: submicron back-gated nanotube transistors fabricated on aligned nanotubes with SiO2 as a gate dielectric and Si as a back-gate; submicron top-gated nanotube transistors on aligned nanotubes with high-.kappa. Al.sub.2O.sub.3 or HfO.sub.2 as a gate dielectric and a metal electrode as atop-gate at a wafer-scale; or submicron individual back-gated nanotube transistors on aligned nanotubes with high-.kappa. Al.sub.2O.sub.3 or HfO.sub.2 as a back-gate dielectric and a metal electrode as an individual back-gate. The wafer can include at least one of CMOS inverters, CMOS NOR logic gates, CMOS NAND logic gates, or ring oscillators.

"The techniques, apparatus and systems described herein can provide one or more of the following advantages. For example, truly integrated high-performance nanotube circuits and wafer-scale fabrication can be fabricated. Technical implementations in fabricating the integrated nanotube circuits and wafer-scale fabrication can include wafer-scale synthesis and transfer of aligned nanotubes, and integrated submicron-scale device fabrication and tuning. In addition, the described techniques, apparatus and systems can be used to provide a defect-tolerant circuit design for integrated nanotube circuits. Additionally, the described techniques, apparatus and systems can be used to produce aligned nanotube devices that can that allow for wafer-scale fabrication and integration; enhance transistor performance; and allow for controlled doping to produce truly integrated circuits with p-type and n-type transistors on one chip. These and other aspects and their exemplary implementations are described in detail in the attached drawings, the description and the claims."

For additional information on this patent, see: Zhou, Chongwu; Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan. Integrated Circuits Based on Aligned Nanotubes. U.S. Patent Number 8778716, filed January 14, 2013, and published online on July 15, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8778716.PN.&OS=PN/8778716RS=PN/8778716

Keywords for this news article include: Emerging Technologies, Nanotechnology, Nanotube, Quartz, Silicon Dioxide, University of Southern California.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Life Science Weekly


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