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New Findings on Computer Research Described by Investigators at Nanyang Technological University (Floorplan Optimization of Fat-Tree-Based...

July 31, 2014

New Findings on Computer Research Described by Investigators at Nanyang Technological University (Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors)

By a News Reporter-Staff News Editor at Computer Weekly News -- Current study results on Computer Research have been published. According to news reporting originating from Singapore, Singapore, by VerticalNews correspondents, research stated, "Chip multiprocessor (CMP) is becoming increasingly popular in the processor industry. Efficient network-on-chip (NoC) that has similar performance to the processor cores is important in CMP design."

Our news editors obtained a quote from the research from Nanyang Technological University, "Fat-tree-based on-chip network has many advantages over traditional mesh or torus-based networks in terms of throughput, power efficiency, and latency. It has a bright future in the development of CMP. However, the floorplan design of the fat-tree-based NoC is very challenging because of the complexity of topology. There are a large number of crossings and long interconnects, which cause severe performance degradation in the network. In electronic NoCs, the parasitic capacitance and inductance will be significant. In optical ones, large crosstalk noise and power loss will be introduced. The novel contribution of this paper is to propose a method to optimize the fat-tree floorplan, which can effectively reduce the number of crossings and minimize the interconnect length. Two types of floorplans are proposed, which could be applied to fat-tree-based networks of arbitrary size. Compared with the traditional one, our floorplans could reduce more than 87% of the crossings."

According to the news editors, the research concluded: "Since the traversal distance for signals is related to the aspect ratio of the processor cores, we also present a method to calculate the optimum aspect ratio of the processor cores to minimize the traversal distance."

For more information on this research see: Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors. IEEE Transactions on Computers, 2014;63(6):1445-1458. IEEE Transactions on Computers can be contacted at: Ieee Computer Soc, 10662 Los Vaqueros Circle, PO Box 3014, Los Alamitos, CA 90720-1314, USA. (Institute of Electrical and Electronics Engineers -; IEEE Transactions on Computers -

The news editors report that additional information may be obtained by contacting Z.H. Wang, Nanyang Technological University, Singapore 639798, Singapore. Additional authors for this research include J. Xu, X.W. Wu, Y.Y. Ye, W. Zhang, M. Nikdast, X. Wang and Z. Wang.

Keywords for this news article include: Singapore, Singapore, Asia, Computer Research

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Source: Computer Weekly News

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