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Patent Issued for System on a Chip Serial Communication Interface Method and Apparatus

July 8, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- Marvell International Ltd. (Hamilton, BM) has been issued patent number 8762608, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Longstreet, Roger (Cheyenne, WY); Khanzode, Vivek Raghunath (Sunnyvale, CA); Sheng, Hongying (San Jose, CA).

This patent was filed on November 5, 2013 and was published online on June 24, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "A typical storage system on a chip (SOC) device has many functional blocks, e.g., a read channel (RC) block, a hard disk controller (HDC) block; a processor block; and static random access memory block (SRAM). For testing the various blocks, the SOC may be programmed into various 'personality' modes. When the SOC is programmed into a personality mode, the definition of digital pins change and the SOC behaves like a discrete device depending on the selected personality mode. In an RC-only mode, the definition of most of the digital pins is changed to pins defined for the RC interface (e.g., the Advanced Technology Attachment (ATA) pins for the normal mode are used as the RC non-return-to-zero (NRZ) pins). This is achieved by multiplexing the block level interface pins out to the SOC pins. While this technique may work for high pin count SOCs (e.g., parallel Advanced Technology Attachment (PATA) SOCs), it may present difficulties with respect to low pin count SOCs.

"Current trends see the SOC pin count, and the driving capability of the pins themselves, reducing. For an enterprise class SOC, the RC inside can easily run at 2.5 gigahertz (GHz) (and faster for the future) and, therefore, the SOC pins need to be able to drive the complementary metal oxide semiconductor (CMOS) signals at approximately 250 megahertz (MHz). In low pin count SOCs, the interface pins are not capable of driving more than 50 MHz digital signals. Also, to provide for ten bits of NRZ data, at least twelve pins are needed, not counting the control interface. It is impractical for the low pin count SOC to spare so many pins."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "In view of the challenges in the state of the art, embodiments of the invention are based on the technical problem of reducing the amount of electrical connections of a system on a chip (SOC) that are used for testing components of the SOC. An SOC, complementary interface, and test unit are provided as suitable to solve the problems upon which at least one embodiment of the invention is based.

"More specifically, there is provided, a method in accordance with various embodiments, in an SOC having a control logic block, a processor block, and a serial communication interface, where the serial communication interface performs operations including receiving a parallel signal stream from a control logic block of the SOC, receiving a personality mode selection signal, and converting the parallel signal stream to a serial signal stream and transmitting the serial signal stream from the SOC based at least in part on the receiving of the personality mode selection signal.

"In various embodiments where the control logic block includes a read channel block (RDC), the method may further include placing the SOC into a RDC-only personality mode, based at least in part on said receiving of the personality mode selection signal, to facilitate testing of the RDC.

"In various embodiments the serial communication interface may perform the operation of transmitting the serial signal stream via a first serial port of the SOC, receiving a second serial signal stream via a second serial port of the SOC, converting the second serial signal stream to a second parallel signal stream, and transmitting the second parallel signal stream to the control logic block. The transmitting of the serial signal may include transmitting the serial signal stream via a pair of differential signal lines coupled to the first serial port.

"Various embodiments may include SOCs that provide suitable solutions to at least some of the above identified challenges found in prior art SOCs. For example, an SOC of some embodiments may include a processor block, a control logic block, which may include an RDC and/or a hard disk controller block (HDC), to output a parallel signal stream, and a serial communication interface communicatively coupled to the control logic block and the processor block. The serial communication interface may receive the parallel signal stream, receive a personality mode selection signal, and convert the parallel signal stream to a serial signal stream and output the serial signal stream based at least in part on the personality mode selection signal.

"In various embodiments, the SOC may comprise a non-return-to-zero (NRZ) bus communicatively coupled to the control logic block and the serial communication interface to transmit at least a portion of the first parallel signal stream from the control logic block to the serial communication interface.

"In various embodiments, the serial communication interface may have an output serial port with a pair of differential electrical connections to output the serial signal stream. The serial communication interface may also have a parallel-to-serial block to convert the parallel signal stream to a serial signal stream. The parallel-to-serial block may include an encoder to encode the parallel signal stream and a transmit PHY block to modulate the encoded parallel signal stream as the serial signal stream for output via the output serial port.

"The serial communication interface may have a input serial port with a pair of differential electrical connections to receive a serial signal stream. In these embodiments the serial communication interface may convert the received serial signal stream to a parallel signal stream, and transmit the parallel signal stream to the control logic block of the SOC.

"In various embodiments, the serial communication interface may additionally receive a parallel signal stream from the processor block of the SOC, convert the processor block's parallel signal stream to serial signal stream and transmit the serial signal stream via the same output serial port used for transmitting the serial signal streams of the RDC and/or HDC.

"The serial communication interface of the SOC of various embodiments may have means for receiving a parallel signal stream from the control logic, which may be the RDC and/or the HDC, means for receiving a personality mode selection signal, means for converting the parallel signal stream to a serial signal stream and transmitting the serial signal stream from the SOC based at least in part on said receiving of the personality mode selection signal.

"In various embodiments, the serial communication interface may include means for placing the SOC into an RDC-only personality mode, based at least in part on said receiving of the personality mode selection signal, to facilitate testing of the RDC.

"In various embodiments, the serial communication interface may include means for receiving a serial signal stream that originates from off the SOC, means for converting the received serial signal stream to a parallel signal stream, and means for transmitting the another parallel signal stream to the control logic block.

"In various embodiments, a testing system for testing components of the SOC may also be described and claimed herein. This testing system may include a test unit to be communicatively coupled to an SOC. The test unit may include a controller to provide a personality mode selection signal to place the SOC into a selected personality mode for testing the control logic block of the SOC.

"The testing system may also include a serial communication interface, external to the SOC, to be communicatively coupled to the SOC and to the test unit. The off-chip serial communication interface may transmit a plurality of signal streams between the SOC and the test unit through a serial interface provided to the SOC and a parallel interface provided to the test unit.

"In various embodiments the off-chip serial communication interface may receive, from the SOC, a serial signal stream, convert the serial signal stream to a parallel signal stream, and transmit the parallel signal stream to the test unit via the parallel interface. The off-chip serial communication interface may additionally/alternatively receive, from the test unit, another parallel signal stream, convert the another parallel signal stream to another serial signal stream, and transmit the another serial signal stream to the SOC via the serial interface.

"Other features that are considered as characteristic for embodiments of the present invention are set forth in the appended claims."

For the URL and additional information on this patent, see: Longstreet, Roger; Khanzode, Vivek Raghunath; Sheng, Hongying. System on a Chip Serial Communication Interface Method and Apparatus. U.S. Patent Number 8762608, filed November 5, 2013, and published online on June 24, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8762608.PN.&OS=PN/8762608RS=PN/8762608

Keywords for this news article include: Technology, Marvell International Ltd..

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Source: Journal of Technology


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