News Column

Patent Issued for Optimizing Logic Synthesis for Environmental Insensitivity

July 8, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- Synopsys, Inc. (Mountain View, CA) has been issued patent number 8762904, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Park, Chaeryung (Saratoga, CA); Sheng, Henry (San Mateo, CA).

This patent was filed on March 28, 2012 and was published online on June 24, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The invention relates to integrated circuit fabrication, and more particularly to logic synthesis techniques that have increased tolerance to build variations.

"An integrated circuit design flow typically proceeds through the following stages: product idea, electronic design automation (EDA), tape-out, fabrication, packing/assembly, and chips. The EDA software stage typically includes steps of System Design, Logic Design and Functional Verification, Synthesis and Design for Test, Design Planning, Netlist Verification, Physical Implementation, Analysis and Extraction, Physical Verfication (DRC, LRC, LVS), Resolution Enhancement (OPC, PSM, Assists), and Mask Data Preparation.

"Logic synthesis typically begins with a logic design which specifies the various functional blocks that are to be implemented on the integrated circuit, and a 'netlist' that indicates the electrical interconnections that are to be made between outputs of each block and inputs of the next. The functional blocks are typically specified in terms of standard cell functions available in a library provided by a fabrication vendor, which are specific to the vendor's fabrication process technology. For most cell functions the library offers a number of different cells optimized for different purposes. It is primarily a task of logic synthesis to select the optimum cell from the library. The selection is usually made on the basis of factors such as minimum and maximum setup and hold times, chip area occupied, and leakage current, and it is an iterative process to select cells that optimize over an entire module or chip.

"As chip designers begin preparing designs for the 28 and 20 nm technology nodes and below, however, circuit behavior is becoming increasingly unpredictable. Aspects of the invention address this problem."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "An opportunity therefore arises to create robust solutions to the problem of unpredictability in the physical implementation of logic designs. Better chip yields, and denser, and more powerful circuits, components and systems may result.

"Roughly described, the invention involves a method for synthesizing a circuit design from a logic design which specifies functional blocks having inputs and outputs and signal paths, including developing candidate solutions for a particular signal path, a first candidate solution identifying, for implementing a particular one of the functional blocks in the path, a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying, for implementing the particular functional block, a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in combination being different from the second library cell and second set of buffers in combination. The computer system selects among the candidate solutions at least in part in dependence upon sensitivity of the solution to load capacitance in the particular path, and stores the selected solution in the storage for subsequent use in further developing and fabricating an integrated circuit device.

"The above summary of the invention is provided in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. Particular aspects of the invention are described in the claims, specification and drawings."

For the URL and additional information on this patent, see: Park, Chaeryung; Sheng, Henry. Optimizing Logic Synthesis for Environmental Insensitivity. U.S. Patent Number 8762904, filed March 28, 2012, and published online on June 24, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8762904.PN.&OS=PN/8762904RS=PN/8762904

Keywords for this news article include: Technology, Synopsys Inc..

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Source: Journal of Technology


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