News Column

Patent Issued for Magnetic Memory Write Circuitry

July 8, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- Avalanche Technology, Inc. (Fremont, CA) has been issued patent number 8760914, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Keshtbod, Parviz (Los Altos Hills, CA).

This patent was filed on December 19, 2012 and was published online on June 24, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates generally to magnetic memory element and particularly to sensing (or reading) of and writing to the magnetic memory element and an array made of the same.

"Computers conventionally use rotating magnetic media, such as hard disk drives (HDDs), for data storage. Though widely used and commonly accepted, such media suffer from a variety of deficiencies, such as access latency, the data not being randomly accessible, higher power dissipation, large physical size and inability to withstand any physical shock. Thus, there is a need for a new type of storage device devoid of such drawbacks.

"Other dominant storage devices are dynamic random access memory (DRAM) and static RAM (SRAM) which are volatile and very costly but have fast random read/write access time. Solid state storage, such as solid-state-nonvolatile-memory (SSNVM) devices having memory structures made of NOR/NAND-based Flash memory, providing fast access time, increased input/output (IOP) speed, decreased power dissipation and physical size and increased reliability but at a higher cost which tends to be generally multiple times higher than hard disk drives (HDDs).

"Although NAND-based flash memory is more costly than HDD's, it has replaced magnetic hard drives in many applications such as digital cameras, MP3-players, cell phones, and hand held multimedia devices due, at least in part, to its characteristic of being able to retain data even when power is disconnected. However, as memory dimension requirements are dictating decreased sizes, scalability is becoming an issue because the designs of NAND-based Flash memory and DRAM memory are becoming difficult to scale with smaller dimensions. For example, NAND-based flash memory has issues related to capacitive coupling, few electrons/bit, poor error-rate performance and reduced reliability due to decreased read-write endurance. Read-write endurance refers to the number of reading, writing and erase cycles before the memory starts to degrade in performance due primarily to the high voltages required in the program, erase cycles. The flash-type non-volatile memories are typically capable of writing one type of data randomly (e.g. 0's), to write other types of data a larger section of the memory needs to be erased.

"It is believed that NAND flash, especially multi-bit designs thereof, would be extremely difficult to scale below 45 nanometers. Likewise, DRAM has issues related to scaling of the trench capacitors leading to very complex designs which are becoming increasingly difficult to manufacture, leading to higher cost.

"Currently, applications commonly employ combinations of EEPROM/NOR, NAND, HDD, and RAM as a part of the memory in a system design. Design of different memory technology in a product adds to design complexity, time to market and increased costs. For example, in hand-held multi-media applications incorporating various memory technologies, such as NAND Flash, DRAM and EEPROM/NOR flash memory, complexity of design is increased as are manufacturing costs and time to market. Another disadvantage is the increase in size of a device that incorporates all of these types of memories therein.

"There has been an extensive effort in development of alternative technologies such as Ovanic Ram (or phase-change memory), Ferromagnetic Ram (FeRAM), current Magnetic Ram (MRAM), Nanochip, and others to replace memories used in current designs such as DRAM, SRAM, EEPROM/NOR flash, NAND flash and HDD in one form or another. Although these various memory/storage technologies have created many challenges, such as requiring too much current or having a large cell size or not readily scalable, there have been advances made in this field in recent years. Current MRAM designs seem to lead the way in terms of its progress in the past few years to replace all types of memories in the system as a universal memory solution.

"An MRAM element generally consists of a magnetic tunnel junction (MTJ) and an access transistor. A magnetic tunnel junction (MTJ) generally consists of a tunneling layer, such as one made of magnesium oxide (MgO) formed between two magnetic layers.

"Electron current tunneling through the tunneling layer depends on the orientation of the two magnetic layers. If the magnetic orientations of the two magnetic layers are parallel, electrons have a relatively easy time tunneling through the tunneling layer, otherwise, tunneling is difficult and some of the electrons are reflected at the interface. Therefore, the total resistance of the MTJ is less when the directions of the magnetic orientation of the magnetic layers are parallel relative to each other. If the resistance of the MTJ is Rl (or R.sub.low) when the magnetic directions are parallel, and Rh (or R.sub.high) when they are anti-parallel, the relative change of resistance is defined as (R.sub.h-R.sub.l)/Rl, which is a measurement of tunneling magnetic resistance (TMR). That is, the following equation defines TMR as: TMR=(Rh-Rl)/Rl Eq. (1)

"The first time a product is manufactured, the magnetic orientations in all the MTJs are typically in the same direction, such as in a parallel state. Therefore, the resistances of all the memory elements are at R.sub.l. After writing a '1' (or an active logic state, which may be considered '0' in certain cases), the resistance changes to R.sub.h. Due to noise and other natural variances in the manufacturing process and write operations, the value of the resistances (R.sub.l or R.sub.h) form a Gaussian distribution around certain R.sub.low.sub.--.sub.avg and R.sub.high.sub.--.sub.avg. In reading a memory cell, which includes a memory element, its resistance is determined and based on its detected resistance, its logical state is determined as being a '0' or '1'. To do so, the memory cell resistance is compared to a resistor with the average value of Ravg=(R.sub.low.sub.--.sub.avg R.sub.high.sub.--.sub.avg)/2. When the R.sub.high-R.sub.avg is larger than a certain value V0 for a particular memory cell, the cell is read as '1', and when R.sub.avg-R.sub.low is larger than V0 for a particular memory cell, the cell is read as '0'. If the values are less than V0, the memory cell state is undetermined and can not be read. The V0 value is related to the sensitivity of the sense amplifier. For instance, the value of V0 is smaller for more sensitive sense amplifier.

"However, one of the problems associated with the foregoing is that the value of the V0 can not be lowered indefinitely because of the presence of thermal noise as well as noise generated by the switching of signals from one state to another. This requires the value of V0 to be larger than Vnoise by several orders of magnitude.

"What is needed is a circuit for reliably sensing and writing to MRAM memory cells."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a design method and a corresponding structure for a magnetic storage memory device that is based on spin current-induced-magnetization-switching having reduced switching current in the magnetic memory.

"Briefly, an embodiment of the present invention includes a sensing circuit having a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

"In another embodiment, a magnetic memory write circuit is disclosed to include a magnetic memory element coupled to a bit line on one end and an access transistor coupled to an opposite end of the magnetic memory element and operative to select the magnetic memory element to be read or written thereto. The access transistor is further coupled to a word line, the magnetic memory element are selected to be read from or written to when the bit line and word line are activated. A first inverter has an output coupled to the bit line and an input coupled to an input of the magnetic memory write circuit and a second inverter has an input coupled to the input of the magnetic memory write circuit and further having an output and a third inverter has an input coupled to the output of the second inverter and an output coupled to the source of the access transistor and to ground.

"These and other objects and advantages of the present invention will no doubt become apparent to those skilled in the art after having read the following detailed description of the preferred embodiments illustrated in the several figures of the drawing."

For the URL and additional information on this patent, see: Keshtbod, Parviz. Magnetic Memory Write Circuitry. U.S. Patent Number 8760914, filed December 19, 2012, and published online on June 24, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8760914.PN.&OS=PN/8760914RS=PN/8760914

Keywords for this news article include: Avalanche Technology Inc..

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Source: Journal of Technology


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