News Column

Patent Issued for Dynamic LDPC Code Rate Solution

July 8, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- A patent by the inventors Hu, Xinde (San Diego, CA); Barndt, Richard D. (San Diego, CA), filed on November 15, 2012, was published online on June 24, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8762798 is assigned to STEC, Inc. (Santa Ana, CA).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Data storage applications (for example, solid state drives, hard disk drives, and the like) may use low density parity check (LDPC) to correct errors that occur when storing and reading, or sending and receiving information. One design choice in planning LDPC coding systems is an amount of redundancy (ECC parity bits) used to meet the product specification. This redundancy is represented by the code rate of an LDPC code, which is equal to the user data length divided by the total number of bits stored. The general trend is that the lower the code rate is (more redundancy added), the better protection of the user data, and better performance in error detection and correction. If the code rate is chosen too high, the device may fail before the targeted program/erasure lifetime due to increasing error rates. On the other hand, if the code rate is chosen too low, extra storage space is wasted. Different LDPC encoder/decoder designs are implemented for different code rates, and for different chips/technologies or applications. Devices from different manufacturers may utilize different code rates, and, in that regard, code rates may span a wide range.

"A flash memory chip has vastly different behavior at the beginning of life ('BOL') and at end of life ('EOL') scenarios. In particular, the data error rates from the flash memory chip increase dramatically as the flash memory chip ages. For example, the raw bit error rate ('BER') produced during read operations may increase by a magnitude of 100 between 1K and 30K program/erase ('P/E') cycles."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A computer-implemented method for adjusting a code rate in a solid-state drive is disclosed. According to one aspect, the method may comprise performing a first plurality of memory operations on a flash memory device using a first code rate, monitoring an operating condition associated with one or more memory units of the flash memory device for a trigger event, adjusting, on the trigger event, the first code rate in accordance with the operating condition to produce a second code rate, and performing a second plurality of memory operations on the flash memory device using the second code rate. Other aspects include corresponding systems, apparatus, and computer program products.

"In another aspect, a machine-readable medium may have instructions stored thereon that, when executed, cause a machine to perform a method of adjusting a code rate in a solid-state drive. In this regard, the method may include receiving a first quantity of host data, encoding, for storage in one or more memory units, a first quantity of host data at a first code rate, the first code rate corresponding to a predetermined code rate value, monitoring one or more operating conditions associated with the one or more memory units for a trigger event, adjusting, on a predetermined trigger event, the code rate value, receiving a second quantity of host data, and encoding, for storage in the one or more memory units, a second quantity of host data at a second code rate.

"In a further aspect, a system includes a flash controller, one or more flash memory devices, and one or more embedded memories associated with the controller. The memories have instructions stored thereon that, when executed, may cause the flash controller to monitor one or more operating conditions associated with the one or more flash memory devices for one or more trigger events, and adjust, on a predetermined trigger event, a code rate used in current memory operations performed by the flash controller by an amount sufficient to reduce, below a predetermined threshold, a read error rate produced in connection with future memory operations.

"It is understood that other configurations of the subject technology will become readily apparent to those skilled in the art from the following detailed description, wherein various configurations of the subject technology are shown and described by way of illustration. As will be realized, the subject technology is capable of other and different configurations and its several details are capable of modification in various other respects, all without departing from the scope of the subject technology. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive."

URL and more information on this patent, see: Hu, Xinde; Barndt, Richard D.. Dynamic LDPC Code Rate Solution. U.S. Patent Number 8762798, filed November 15, 2012, and published online on June 24, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8762798.PN.&OS=PN/8762798RS=PN/8762798

Keywords for this news article include: STEC Inc., Technology.

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Source: Journal of Technology


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