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Patent Application Titled "Method and Video Decoder for Decoding Scalable Video Stream Using Inter-Layer Racing Scheme" Published Online

July 8, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Liu, Tsu-Ming (Hsinchu City, TW); Chang, Yung-Chang (New Taipei City, TW); Ju, Chi-Cheng (Hsinchu City, TW), filed on August 3, 2011, was made available online on June 26, 2014.

No assignee for this patent application has been made.

Reporters obtained the following quote from the background information supplied by the inventors: "Advances in video coding technology and standardization along with the rapid developments and improvements of network infrastructures, storage capacity, and computing power enable an increased number of video applications nowadays. The video transmission systems using the Internet and mobile communication networks are for real-time services characterized by a wide range of connection qualities and receiving devices. For example, the receiving devices with different capabilities may range from cell phones with small display screens and restricted computing power to high-end personal computers with high-definition display apparatuses and powerful computing power. Regarding the problems encountered by the characteristics of the above-mentioned video transmission systems, scalable video coding (SVC) may be a highly attractive solution for video frame transmission.

"SVC is an extension of the H.264/AVC standard and standardizes the encoding of a high-quality video bitstream that also contains one or more subset bitstreams. The subset bitstream can represent a lower spatial resolution (smaller screen), lower temporal resolution (lower frame rate), or a lower video quality compared to the bitstream it is derived from. For example, the spatial scalability over H.264/SVC may allow 8 layers for different spatial resolutions at most. Besides, the inter-layer dependency may be exploited for improving the coding efficiency. Preferably, a low-resolution layer (e.g., a base layer) is referenced by a high-resolution layer (e.g., an enhancement layer) when the high-resolution layer is being coded at a video encoder. Therefore, inter-layer intra prediction, inter-layer residual prediction, and/or inter-layer motion prediction may be employed by the video encoder for generating coded enhancement layer frames.

"Regarding the decoding flow performed at a video decoder, the conventional design fully decodes a base layer frame to generate a complete decoding result, store the complete decoding result into an external memory, and decoding an enhancement layer frame by reading information provided by the complete decoding result stored in the external memory. However, such a conventional design of decoding an enhancement layer frame requires a large storage capacity for buffering a complete decoding result of a base layer frame and a large bandwidth for accessing an external memory."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "In accordance with exemplary embodiments of the present invention, a method for decoding a scalable video stream (e.g., an H.264/SVC stream) using an inter-layer racing scheme and related video decoder thereof are proposed to solve the above-mentioned problem.

"According to a first aspect of the present invention, an exemplary method for decoding a scalable video stream including a base layer frame and at least an enhancement layer frame corresponding to the base layer frame is disclosed. The exemplary method includes: decoding the base layer frame; and before the base layer frame is fully decoded, decoding the enhancement layer frame.

"According to a second aspect of the present invention, an exemplary method for decoding a scalable video stream including a base layer frame and at least an enhancement layer frame corresponding to the base layer frame is disclosed. The exemplary method includes: decoding the enhancement layer frame, and decoding the base layer frame, wherein a start point of decoding the enhancement layer frame is earlier than a start point of decoding the base layer frame.

"According to a third aspect of the present invention, an exemplary video decoder for decoding a scalable video stream including a base layer frame and at least an enhancement layer frame corresponding to the base layer frame is disclosed. The exemplary video decoder includes a base layer decoding circuit arranged for decoding the base layer frame; and an enhancement layer decoding circuit arranged for decoding the enhancement layer frame before the base layer frame is fully decoded by the base layer decoding circuit.

"According to a fourth aspect of the present invention, an exemplary video decoder for decoding a scalable video stream including a base layer frame and at least an enhancement layer frame corresponding to the base layer frame is disclosed. The exemplary video decoder includes: an enhancement layer decoding circuit arranged for decoding the enhancement layer frame; and a base layer decoding circuit arranged for decoding the base layer frame. The enhancement layer decoding circuit starts decoding the enhancement layer frame before the base layer decoding circuit starts decoding the base layer frame.

"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

"FIG. 1 is a block diagram illustrating a video decoder employing a base layer racing mode according to an exemplary embodiment of the present invention.

"FIG. 2 is a diagram illustrating the decoding of a current macroblock within the base layer frame.

"FIG. 3 is a diagram illustrating a reference layer macroblock with D=1 and R=0.5 under a frame mode supporting cropping and another reference layer macroblock with D=0.5 and R=1 under a frame mode supporting an arbitrary ratio mode.

"FIG. 4 is a diagram illustrating a reference layer macroblock with D=1 and R=0.5 under a frame/filed coding mode.

"FIG. 5 is a diagram illustrating a comparison between a conventional video decoder design and a video decoder of the present invention that employs a base layer racing mode in which the base layer races first.

"FIG. 6 is a block diagram illustrating a video decoder employing an enhancement layer racing mode according to an exemplary embodiment of the present invention.

"FIG. 7 is a diagram illustrating an exemplary storage arrangement of syntax elements in the prediction mode information storage device shown in FIG. 6.

"FIG. 8 is a diagram illustrating an access behavior of the first data storage and the second data storage device when the inter-layer prediction is needed.

"FIG. 9 is a diagram illustrating an access behavior of the first data storage and the second data storage device when the inter-layer prediction is not needed.

"FIG. 10 is a diagram illustrating a comparison between a conventional video decoder design and a video decoder of the present invention that employs an enhancement layer racing mode in which the enhancement layer races first."

For more information, see this patent application: Liu, Tsu-Ming; Chang, Yung-Chang; Ju, Chi-Cheng. Method and Video Decoder for Decoding Scalable Video Stream Using Inter-Layer Racing Scheme. Filed August 3, 2011 and posted June 26, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4332&p=87&f=G&l=50&d=PG01&S1=20140619.PD.&OS=PD/20140619&RS=PD/20140619

Keywords for this news article include: Patents, Information Technology, Information and Data Storage.

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Source: Information Technology Newsweekly


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