News Column

Patent Application Titled "Joint Logical and Physical Address Remapping in Non-Volatile Memory" Published Online

July 8, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventor Schwartz, Yair (Yokneam Ilit, IL), filed on December 19, 2012, was made available online on June 26, 2014.

The assignee for this patent application is Apple Inc.

Reporters obtained the following quote from the background information supplied by the inventors: "Various types of data storage systems use logical-to-physical address translation. In such systems, data is provided for storage in specified logical addresses, and the logical addresses are translated into respective physical addresses in which the data is physically stored. Address translation schemes of this sort are used, for example, in Flash Translation Layers (FTL) that manage data storage in Flash memory."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventor's summary information for this patent application: "An embodiment of the present invention that is described herein provides a method including, for data items that are to be stored in a non-volatile memory in accordance with respective logical addresses, associating the logical addresses with respective physical storage locations in the non-volatile memory, and storing the data items in the respective associated physical storage locations. A remapping command, which specifies a group of source logical addresses that are associated with respective source physical storage locations, is received. In response to the remapping command, destination physical storage locations and destination logical addresses are selected jointly for replacing the source physical storage locations and the source logical addresses, respectively, so as to meet a joint performance criterion with respect to the logical addresses and the physical storage locations. The data items are copied from the source physical storage locations to the respective destination physical storage locations, and the destination physical storage locations are re-associated with the respective destination logical addresses.

"In some embodiments, jointly selecting the destination physical storage locations and the destination logical addresses includes reducing a first number of logical memory fragments occupied by the destination logical addresses relative to the source logical addresses, and reducing a second number of physical memory fragments occupied by the destination physical storage locations, relative to the source physical storage locations.

"In an embodiment, jointly selecting the destination physical storage locations and the destination logical addresses includes increasing a throughput of accessing the data items in the non-volatile memory. In another embodiment, jointly selecting the destination physical storage locations and the destination logical addresses includes reducing a latency of accessing the data items in the non-volatile memory.

"In a disclosed embodiment, jointly selecting the destination physical storage locations and the destination logical addresses includes selecting the destination logical addresses in a first contiguous sequence, and selecting the respective destination physical storage locations in a second contiguous sequence. In an alternative embodiment, the non-volatile memory includes multiple memory units, and jointly selecting the destination physical storage locations and the destination logical addresses includes selecting the destination logical addresses in a contiguous sequence, and selecting the respective destination physical storage locations in cyclical alternation among the multiple memory units.

"In yet another embodiment, jointly selecting the destination physical storage locations and the destination logical addresses includes increasing a compressibility of a data structure used for storing respective associations between the logical addresses and the physical storage locations. In still another embodiment, receiving the remapping command includes receiving an indication of the destination logical addresses in the command.

"In some embodiments, the remapping command does not indicate the destination logical addresses, and jointly selecting the destination physical storage locations and the destination logical addresses includes deciding the destination logical addresses in response to receiving the command. The method may include outputting a notification of the decided destination logical addresses. In an embodiment, jointly selecting the destination physical storage locations and the destination logical addresses includes identifying an idle time period, and choosing the destination physical storage locations and the destination logical addresses during the idle time period.

"There is additionally provided, in accordance with an embodiment of the present invention, apparatus including an interface and a processor. The interface is configured for communicating with a non-volatile memory. The processor is configured, for data items that are to be stored in the non-volatile memory in accordance with respective logical addresses, to associate the logical addresses with respective physical storage locations in the non-volatile memory and to store the data items in the respective associated physical storage locations, to receive a remapping command, which specifies a group of source logical addresses that are associated with respective source physical storage locations, to jointly select, in response to the remapping command, destination physical storage locations and destination logical addresses for replacing the source physical storage locations and the source logical addresses, respectively, so as to meet a joint performance criterion with respect to the logical addresses and the physical storage locations, to copy the data items from the source physical storage locations to the respective destination physical storage locations, and to re-associate the destination physical storage locations with the respective destination logical addresses.

"The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

"FIG. 2 is a diagram that schematically illustrates a joint logical and physical address remapping process, in accordance with an embodiment of the present invention; and

"FIG. 3 is a flow chart that schematically illustrates a method for joint logical and physical address remapping, in accordance with an embodiment of the present invention."

For more information, see this patent application: Schwartz, Yair. Joint Logical and Physical Address Remapping in Non-Volatile Memory. Filed December 19, 2012 and posted June 26, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=621&p=13&f=G&l=50&d=PG01&S1=20140619.PD.&OS=PD/20140619&RS=PD/20140619

Keywords for this news article include: Apple Inc., Information Technology, Information and Data Storage.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Information Technology Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters