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United States : Ricoh Cuts Parasitic Extraction Design Closure Time in Half Using Cadence Quantus QRC Extraction Solution

July 17, 2014



Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that Ricoh Corporation, Ltd. implemented Cadence Quantus QRC Extraction Solution after a rigorous competitive evaluation. By using Cadence s next-generation parasitic extraction solution for all large-scale, complex digital designs and mixed signal power management ICs for their mobile products, Ricoh has cut its design flow parasitic extraction time in half for system-on-chip (SoC) designs.

As a key contributor in realizing a smart-energy society by providing analog semiconductors led by high value-add power management IC products, the Electronic Devices Division of Ricoh is very keen on improving quality and performance. Through our evaluation, we found the Quantus QRC Extraction Solution delivered tighter accuracy, better capacity handling, performance, and signoff flow turnaround time, said Keiichi Yoshioka, general manager, First Development Department Electronic Devices Division at Ricoh Corporation. Furthermore, because Quantus QRC Extraction Solution seamlessly integrates with our installed Cadence Encounter Design Implementation System, we get closer correlation between implementation and signoff, a reduction in unnecessary design cycles and ensured on-time tapeout.

Quantus QRC Extraction Solution is targeted for digital and custom analog flows. The tool features a massively parallel architecture for top performance and scalability across hundreds of CPUs. Its high-accuracy modeling engine has been significantly enhanced to support FinFET designs and uses the same foundry-qualified qrctechfiles for digital and transistor extraction. Its incremental extraction functionality reduces design closure time by performing extraction solely on changed nets rather than requiring a re-extraction of the entire design. The solution, employing a robust 3D modeling framework, is fully certified down to 16nm FinFET processes.


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Source: TendersInfo (India)


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