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Researchers Submit Patent Application, "High Tilt Angle plus Twist Drain Extension Implant for Chc Lifetime Improvement", for Approval

July 24, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Bo, Xiang-Zheng (Plano, TX); Tsao, Alwin (Garland, TX); Grider, Douglas T. (McKinney, TX), filed on December 27, 2013, was made available online on July 10, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Some integrated circuits contain analog metal oxide semiconductor (MOS) transistors which have drain extensions in a substrate of the integrated circuit adjacent to, and extending partway under, gates of the analog MOS transistors. The analog MOS transistors have no halo implanted regions. It is desirable to implant dopants to form the drain extensions so as to provide laterally graded junctions to obtain channel hot carrier (CHC) reliability. Implants to form the drain extensions are angled at a tilt angle (referenced to a perpendicular line to a top surface of the integrated circuit) to produce a graded junction that extends a desired distance under the gates. The angled implants typically have tilt angles of 25 degrees to 30 degrees, with zero twist angles, that is, the implants are perpendicular to source/drain edges of the gates. The implants are performed in a series of four sub-implants with equal doses and rotated by 90 degrees for each sub-implant to provide symmetric implants with uniform dosing on all sides of all the analog MOS transistors. However, some integrated circuits are dense, so that an implant mask, typically photoresist, blocks the angled implant with zero twist from reaching the substrate at the source/drain edges of the gates. For these cases, the implants are performed in a series of four sub-implants at twist angles of 45 degrees, which provides more CHC reliability than the zero twist implants, but results in less CHC reliability than desired."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.

"An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants implant the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. Two of the sub-implants are blocked from the source/drain gate edge by a gate of the analog MOS transistor. All four sub-implants are performed at a same tilt angle of at least 15 degrees, referenced to a perpendicular line to a top surface of a substrate of the integrated circuit, which is sufficient for the at least one sub-implant to clear an implant mask and implant the dopants in the substrate at the source/drain gate edge, for each source/drain gate edge of the analog MOS transistor. No halo implants are performed on the analog MOS transistor.

"An integrated circuit containing a first analog MOS transistor and a second analog MOS transistor, wherein source/drain gate edges of the first and second analog MOS transistors are all substantially parallel to one another, may be formed by implanting drain extensions with exactly four sub-implants. Two sub-implants implant dopants in a substrate of the integrated circuit at a source/drain gate edge of the first and second analog MOS transistors, each at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge, and two of the sub-implants are blocked from the source/drain gate edge by a gate of the analog MOS transistor, for each source/drain gate edge. All four sub-implants are performed at a same tilt angle of at least 15 degrees which is sufficient for the sub-implants to clear an implant mask and implant the dopants in the substrate at the relevant source/drain gate edge. No halo implants are performed on the first and second analog MOS transistors.

"An integrated circuit containing a first analog MOS transistor and a second analog MOS transistor, wherein source/drain gate edges of the first analog MOS transistor are substantially perpendicular to source/drain gate edges of the second analog transistor, may be formed by implanting drain extensions with exactly four sub-implants. One sub-implant implants dopants in a substrate of the integrated circuit at a first source/drain gate edge of the first analog MOS transistor, at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the first source/drain gate edge, one sub-implant implants dopants in the substrate at the first source/drain gate edge at a twist angle having a magnitude of 50 degrees to 85 degrees, and two of the sub-implants are blocked from the first source/drain gate edge by a gate of the first analog MOS transistor. Similarly, the substrate at a second source/drain gate edge receives dopants from another of the four sub-implants at a twist angle having a magnitude of 5 degrees to 40 degrees, and another at a twist angle having a magnitude of 50 degrees to 85 degrees, while the remaining two sub-implants are blocked by the gate. Analogously, a first source/drain gate edge of the second analog MOS transistor receives dopants from one of the four sub-implants at a twist angle having a magnitude of 5 degrees to 40 degrees, and one at a twist angle having a magnitude of 50 degrees to 85 degrees, while the remaining two sub-implants are blocked by the gate, and similarly for a second source/drain gate edge of the second analog MOS transistor. All four sub-implants are performed at a same tilt angle of at least 15 degrees which is sufficient for the sub-implants to clear an implant mask and implant the dopants in the substrate at the relevant source/drain gate edge. No halo implants are performed on the first and second analog MOS transistors.

DESCRIPTION OF THE VIEWS OF THE DRAWING

"FIG. 1A and FIG. 1B are cross sections of an integrated circuit containing an analog MOS transistor, formed according to an example method, depicted in successive stages of fabrication.

"FIG. 2 is a top view of an integrated circuit containing a first analog MOS transistor and a second analog MOS transistor which are parallel to each other, during an implant process to form drain extensions.

"FIG. 3 is a top view of an integrated circuit containing a first analog MOS transistor and a second analog MOS transistor which are parallel to each other, during an implant process to form drain extensions.

"FIG. 4 is a top view of an integrated circuit containing a first analog MOS transistor and a second analog MOS transistor which are perpendicular to each other, during an implant process to form drain extensions.

"FIG. 5 is a top view of an integrated circuit containing a first analog MOS transistor and a second analog MOS transistor which are perpendicular to each other, during an implant process to form drain extensions."

For additional information on this patent application, see: Bo, Xiang-Zheng; Tsao, Alwin; Grider, Douglas T. High Tilt Angle plus Twist Drain Extension Implant for Chc Lifetime Improvement. Filed December 27, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2914&p=59&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Patents.

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Source: Politics & Government Week


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