The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The semiconductor industry is producing more and more capable components with smaller and smaller feature sizes. Due to the increased demand for highly integrated semiconductor devices, advanced techniques of fabricating more semiconductor devices in a smaller die area have become strongly relied upon. The production of such semiconductor devices reveals new design and manufacturing challenges to be addressed in order to maintain or improve semiconductor device performance.
"As the device density of semiconductors increases, the conductor line width and spacing within the semiconductor devices decreases. Multiple-pattern lithography represents a class of technologies developed for photolithography to enhance the feature density of semiconductor devices. Double-patterning, a subset of multiple-patterning, may be used as early as the 45 nm node in the semiconductor industry and may be the primary technique for the 32 nm node and beyond. Double-patterning employs multiple masks and photolithographic steps to create a particular level of a semiconductor device. With benefits such as tighter pitches and narrower wires, double-patterning alters relationships between variables related to semiconductor device wiring and wire quality to sustain performance."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In an embodiment, this disclosure relates to a multiple-patterned semiconductor device. The semiconductor device may include one or more layers. A particular level of the semiconductor device may include signal tracks defined by different masks and exposures. The semiconductor device may include a structure which may transfer and repower a signal. Aspects may assist in achieving a timing tolerance standard for carrying a signal on a semiconductor device. Aspects may take into account less than ideal wires. Aspects may assist in preserving signal quality. Aspects may take into account space limitations. Aspects of the disclosure may not add aspects increasing space required for a semiconductor device to operate properly. In an embodiment, aspects may use one layer of a semiconductor device. In other embodiments, aspects may use multiple layers of a semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a planar view showing double-patterned signal tracks carrying wires, repeater structure locations, and example signal paths pursuant to the disclosure; and
"FIG. 2 is a planar view of a repeater structure which may both repower a signal and transfer a signal to a different signal track pursuant to the disclosure.
"FIG. 3 is a planar view of a switch of a semiconductor device which may transfer a signal to a different signal track pursuant to the disclosure.
"FIG. 4 is a flow chart illustrating an operation routing and criss-crossing signals on signal paths according to an embodiment.
"FIG. 5 illustrates multiple design structures including an input design structure that is preferably processed by a design process."
For additional information on this patent application, see: Allen, David H.; Dewanz, Douglas M.;
Keywords for this news article include: Electronics, Semiconductor,
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