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Researchers Submit Patent Application, "Semiconductor Device with High Voltage Transistor", for Approval

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor CHA, Jae-Yong (Gyeonggi-do, KR), filed on March 16, 2013, was made available online on July 10, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device with a high voltage transistor.

"In a design of a transistor to which a high-level voltage is supplied (hereafter, referred to as a high voltage transistor), to prevent a contact melting phenomenon, regulations on the layout of the high voltage transistor have been enacted and complied. Hereinafter, the high voltage refers to a voltage high enough to melt a contact when the voltage is supplied to one end of the contact and a ground voltage is supplied to the other end of the contact. In general, the level of the high voltage may be at least 3V, and may be about 20V at its highest level. The high voltage is generated in the semiconductor device through charge pumping using a power supply voltage that is input from an outside of the semiconductor device.

"FIGS. 1A to 1C are layout views illustrating a forbidden layout (FIG. 1A) and recommended layouts (FIGS. 1B and 1C). Further, FIGS. 2A to 2C are circuit diagrams illustrating transistors 110 and 120 shown in FIGS. 1A to 1C, respectively.

"Referring to FIG. 1A, a high voltage VPP is supplied to one junction 111 of a drain and a source of the transistor 110, and a ground voltage VSS is supplied to the other junction 112 thereof. Further, the high voltage VPP is supplied to one junction 121 of a drain and a source of the transistor 120, and the ground voltage VSS is supplied to the other junction 122 thereof. A voltage INPUT_A is supplied to a gate of the transistor 110 and a voltage INPUT_B is supplied to a gate of the transistor 120. The junction 112 of the transistor 110, to which the ground voltage VSS is supplied, and the junction 121 of the transistor 120, to which the high voltage VPP is supplied, are adjacent to each other. Since the voltage difference between the adjacent junctions 112 and 121 is as high as the high voltage VPP, the contact melting may occur between the junctions 112 and 121, and thus the layout shown in FIG. 1A is not used.

"Referring to FIG. 13, the junction 111 of the transistor 110 and the junction 121 of the transistor 120 are shared. Since the high voltage VPP is identically supplied to the junctions 111 and 121, the voltage difference between the junctions 111 and 121 becomes 0V. Accordingly, in the layout of FIG. 1B, the contact melting may not occur, and the layout is used as a recommended layout (or guide layout).

"Referring to FIG. 1C, the junction 112 of the transistor 110 and the junction 122 of the transistor 120 are disposed adjacent to each other. Since the voltage difference between the adjacent junctions 112 and 122 is 0V, the contact melting may not occur in the layout. Accordingly, the layout shown in FIG. 1C is also used as the recommended layout. For reference, the junctions 112 and 122 of the transistors 110 and 120 may be designed to be shared.

"As described above, the high voltage transistor should be designed along the recommended layout to avoid the forbidden layout. However, in the case where the design is made to be complied with only the recommended layout, there are many limitations in the degree of freedom of the design, and more fundamental solution to the above concerns is in demand."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Exemplary embodiments of the present invention are directed to a semiconductor device that may heighten the degree of freedom in designing a high voltage transistor.

"In an embodiment, a semiconductor device may include a first transistor, a second transistor connected in series to the first transistor through a first junction, and a third transistor connected in series to the second transistor through a second junction. Here, a high voltage is supplied to one of the first junction and second junctions, and a turn-off voltage is supplied to a gate of the second transistor.

"In an embodiment, a semiconductor device may include a first transistor having a first junction to which a high voltage is supplied, a second transistor sharing a first junction with the first transistor and having a gate to which a turn-off voltage is supplied, and a third transistor sharing a second junction of the second transistor.

"In an embodiment, a semiconductor device may include a first dummy transistor formed on a substrate, a first transistor formed on the substrate and sharing a first junction with the first dummy transistor, and a second transistor formed on the substrate and sharing a second junction with the first dummy transistor. Here, a high voltage is supplied to one of the first junction and the second junction of the first dummy transistor, and the first dummy transistor is kept in a turn-off state.

"In accordance with the embodiments of the present invention, the contact melting between the adjacent junctions may be prevented using the transistor that keeps the turn-off state, and thus the degree of freedom of circuit design using the high voltage transistors may be increased.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIGS. 1A to 1C are layout views illustrating a forbidden layout and recommended layouts.

"FIGS. 2A to 2C are circuit diagrams illustrating transistors shown in FIGS. 1A to 1C, respectively.

"FIG. 3 is a layout view illustrating the configuration of a semiconductor device in accordance with an embodiment of the present invention.

"FIG. 4 is a circuit diagram illustrating the semiconductor device shown in FIG. 3.

"FIG. 5 is a layout view illustrating the configuration of a semiconductor device in accordance with another embodiment of the present invention.

"FIG. 6 is a circuit diagram illustrating the semiconductor device shown in FIG. 5.

"FIG. 7 is a cross-sectional view illustrating transistors shown in FIG. 5."

For additional information on this patent application, see: CHA, Jae-Yong. Semiconductor Device with High Voltage Transistor. Filed March 16, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6278&p=126&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Electronics, High Voltage, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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