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Researchers Submit Patent Application, "Memory Systems Including an Input/Output Buffer Circuit", for Approval

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Jeon, Youngjin (Hwaseong-si, KR); Ihm, Jeongdon (Seongnam-sl, KR); Kim, Kilsoo (Hwaseong-si, KR); Han, Jinman (Seongnam-si, KR), filed on December 30, 2013, was made available online on July 10, 2014.

The patent's assignee is Samsung Electronics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to memory systems. A semiconductor memory device may be volatile or nonvolatile. A nonvolatile semiconductor memory device may retain contents stored therein even at power-off Data stored at the nonvolatile semiconductor memory device may be permanent or reprogrammable according to a memory manufacturing technology. The nonvolatile semiconductor memory device may be used to store programs, micro codes, user data in a wide range of applications such as computers, avionics, communications, consumer electronics, and so on."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Various embodiments of the present inventive concepts provide a memory system. The memory system may include a nonvolatile memory package. The memory system may include a memory controller configured to control the nonvolatile memory package. The nonvolatile memory package may include groups of nonvolatile memory devices respectively connected to internal data channels. The memory system may include an input/output buffer circuit configured to connect a data channel to one of the internal data channels when data signals are input to or output from the memory controller via the data channel. The input/output buffer circuit may include an input/output unit configured to operate in a program operation. The input/output unit may include a receiver configured to receive the data signals from the memory controller. The input/output unit may include a sampler configured to sample the data signals from the receiver in response to a data strobe signal to output internal data signals. The input/output unit may include a delay locked loop circuit configured to generate an internal data strobe signal by performing delay synchronization on the data strobe signal. The input/output unit may include a de-multiplexer configured to connect the data channel to one of the internal data channels based on at least one control signal input from the memory controller. The input/output unit may include output drivers configured to receive the internal data signals output from the sampler via the de-multiplexer and to output the internal data signals to the one of the internal data channels connected to the data channel. Moreover, the internal data strobe signal and the internal data signals may be output to one of the groups of nonvolatile memory devices.

"In various embodiments, the nonvolatile memory devices may include stacked nonvolatile memory devices. In some embodiments, the input/output buffer circuit may be directly connected to the stacked nonvolatile memory devices via wire bonding. In some embodiments, the input/output buffer circuit and the stacked nonvolatile memory devices may be connected via a printed circuit board, where at least one of the stacked nonvolatile memory devices may on the printed circuit board, and where the input/output buffer circuit and the stacked nonvolatile memory devices may have a side-by-side structure.

"According to various embodiments, the nonvolatile memory package and the memory controller may be in a chip on a printed circuit board. In some embodiments, the nonvolatile memory package and the memory controller be separate chips, respectively. Moreover, the memory controller may be on a printed circuit board.

"In various embodiments, the input/output buffer circuit may include a temperature measuring unit configured to measure a temperature of the nonvolatile memory package and to transfer temperature information corresponding to the temperature to the memory controller.

"According to various embodiments, the input/output unit may include a first input/output unit, the receiver may include a first receiver, the data signals may include first data signals, the at least one control signal may include at least one first control signal, the delay locked loop circuit may include a first delay locked loop circuit, the internal data strobe signal and the data strobe signal may include a first internal data strobe signal and a first data strobe signal, respectively, and the output drivers may include first output drivers. Moreover, the input/output buffer circuit may include a second input/output unit configured to operate in a read operation. The second input/output unit may include a second receiver configured to receive second internal data signals from one of the groups of nonvolatile memory devices connected to a first or second one of the internal data channels. The input/output buffer circuit may include a multiplexer configured to connect the data channel to the first or second one of the internal data channels based on at least one second control signal input from the memory controller. The input/output buffer circuit may include a second delay locked loop circuit configured to generate a second data strobe signal by delay synchronizing a second internal data strobe signal output from the one of the groups of nonvolatile memory devices connected to the first or second one of the internal data channels. The input/output buffer circuit may include a second sampler configured to receive the second internal data signals output from the second receiver via the multiplexer and to sample the second internal data signals in response to the second data strobe signal to output second data signals. The input/output buffer circuit may include second output drivers configured to output the second data signals that are output from the second sampler, to the data channel, and configured to output the second data strobe signal.

"In various embodiments, the input/output buffer circuit may be configured to, in the program operation or a read operation, sample data signals in response to a clock transferred from the memory controller to input and output the sampled data signals. In some embodiments, the internal data channels may include a first internal data channel and a second internal data channel In some embodiments, the input/output buffer circuit may include a re-timing circuit configured to connect the data channel to the first internal data channel or the second internal data channel in response to a selection signal during the program operation or a read operation. In some embodiments, the input/output buffer circuit may include a status decision logic circuit configured to receive a control signal from the memory controller and to generate the selection signal using the control signal. Moreover, in some embodiments, the input/output buffer circuit may include a read enable pad configured to receive a read enable signal from the memory controller, and may include first and second internal read enable pads connected to the read enable pad via at least one output driver.

"A memory system, according to various embodiments, may include a nonvolatile memory package. The memory system may include a memory controller connected to the nonvolatile memory package via a plurality of channels and configured to control the nonvolatile memory package. The nonvolatile memory package may include first and second internal data channels corresponding to each of the channels, first nonvolatile memory devices connected to the first internal data channel, second nonvolatile memory devices connected to the second internal data channel, and an input/output buffer circuit configured to select one of the first and second internal data channels for inputting and outputting data signals when the data signals are input and output through one of the channels.

"According to various embodiments, the memory controller may include a solid state drive (SSD) controller. The input/output buffer circuit may include at least one delay locked loop circuit. Moreover, the nonvolatile memory package may include a temperature measuring unit configured to measure a temperature of the nonvolatile memory package and to transfer temperature information corresponding to the temperature to the SSD controller.

"A memory system, according to various embodiments, may include a plurality of nonvolatile memories. The memory system may include a memory controller configured to control the plurality of nonvolatile memories. The memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. The memory system may include a data channel connected between the memory controller and the input/output buffer circuit. The memory system may include first and second internal data channels connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. Moreover, the input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

"According to various embodiments, the input/output buffer circuit may be configured to provide at least one data signal from at least one of the plurality of nonvolatile memories to the memory controller, via the one of the first and second internal data channels and the data channel In some embodiments, the input/output buffer circuit may be configured to provide at least one data signal from the memory controller to at least one of the plurality of nonvolatile memories, via the data channel and the one of the first and second internal data channels.

"In various embodiments, the input/output buffer circuit may include a temperature measuring unit configured to measure a temperature of a nonvolatile memory package including the plurality of nonvolatile memories and to transfer temperature information corresponding to the temperature to the memory controller.

"According to various embodiments, the input/output buffer circuit may include a first input/output unit configured to operate in a program operation. The first input/output unit may include a first receiver configured to receive data signals from the memory controller. The first input/output unit may include a first sampler configured to sample the data signals from the first receiver in response to a first data strobe signal to output first internal data signals. The first input/output unit may include a first delay locked loop circuit configured to generate a first internal data strobe signal by performing delay synchronization on the first data strobe signal. The first input/output unit may include a de-multiplexer configured to connect the data channel to one of the first and second internal data channels in response to at least one first control signal input from the memory controller. The first input/output unit may include first output drivers configured to receive the first internal data signals output from the first sampler via the de-multiplexer and to output the first internal data signals to the one of the first and second internal data channels connected to the data channel. The first internal data strobe signal and the first internal data signals may be output to one of the first and second groups of the plurality of nonvolatile memories. Moreover, input/output buffer circuit may include a second input/output unit configured to operate in a read operation. The second input/output unit may include a second receiver configured to receive second internal data signals from one of the first and second groups of the plurality of nonvolatile memories. The second input/output unit may include a multiplexer configured to connect the data channel to one of the first and second internal data channels based on at least one second control signal input from the memory controller. The second input/output unit may include a second delay locked loop circuit configured to generate a second data strobe signal by delay synchronizing a second internal data strobe signal output from the one of the first and second groups of the plurality of nonvolatile memories from which the second receiver receives the second internal data signals. The second input/output unit may include a second sampler configured to receive the second internal data signals output from the second receiver via the multiplexer and to sample the second internal data signals in response to the second data strobe signal to output second data signals. Moreover, the second input/output unit may include second output drivers configured to output the second data signals that are output from the second sampler, to the data channel, and configured to output the second data strobe signal.

"With various embodiments of the present inventive concepts, capacitance of nonvolatile memory devices seen from a controller may be reduced through an input/output buffer circuit which connects a data channel to one of a plurality of internal data channels at a write and a read operation. Thus, although an operating speed may be faster and a data capacity may increase, a memory system according to various embodiments of the present inventive concepts may reduce distortion of data signals.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other features and advantages of the disclosure will become more apparent in view of the attached drawings and accompanying detailed description.

"FIG. 1 is diagram schematically illustrating a memory system according to various embodiments of the present inventive concepts.

"FIG. 2 is a diagram schematically illustrating a stack structure of a nonvolatile memory package according to various embodiments.

"FIG. 3 is a diagram schematically illustrating a first input/output unit of an input/output buffer circuit in a program operation according to various embodiments.

"FIG. 4 is a diagram schematically illustrating a second input/output unit of an input/output buffer circuit in a read operation according to various embodiments.

"FIG. 5 is a block diagram schematically illustrating an input/output buffer circuit when a nonvolatile memory device is a NAND flash memory.

"FIG. 6 is a diagram schematically illustrating a memory system according to various embodiments.

"FIG. 7 is a block diagram schematically illustrating a solid state drive (SSD) according to various embodiments.

"FIG. 8 is a block diagram schematically illustrating an embedded multimedia card (eMMC) according to various embodiments.

"FIG. 9 illustrates a nonvolatile memory package with a side-by-side structure according to various embodiments."

For additional information on this patent application, see: Jeon, Youngjin; Ihm, Jeongdon; Kim, Kilsoo; Han, Jinman. Memory Systems Including an Input/Output Buffer Circuit. Filed December 30, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4533&p=91&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Circuit Board, Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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