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Researchers Submit Patent Application, "Ion Implantation Methods", for Approval

July 23, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors XU, Cheng-Bai (Southborough, MA); WU, Cheng Han (Marlborough, MA); CHUNG, Dong Won (Gyeonggi-do, KR); YAMAMOTO, Yoshihiro (Niigata-Shi, JP), filed on December 31, 2013, was made available online on July 10, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "The invention relates generally to the manufacture of electronic devices. More specifically, this invention relates to methods of forming ion implanted regions in a semiconductor device.

"In the semiconductor manufacturing industry, ion implantation is conventionally used for introducing impurities (or dopants) of a desired conductivity into semiconductor substrates such as silicon wafers. Commonly used impurities include boron (p-type), arsenic (n-type) and phosphorus (n-type). When implanted into a semiconductor, the dopant atoms create charge carriers after annealing. Holes are created for p-type dopants and electrons for n-type dopants, thereby allowing for modification of conductivity of the semiconductor material. The process is thereby used to form and impart desired characteristics to electronic devices such as MOSFETs.

"The ion implantation process involves generation of an ion beam containing the dopant in ionized form from a source, typically in gas or solid form, which is directed to the semiconductor substrate surface. To selectively introduce the impurity atoms into predefined regions of the substrate, a photoresist mask is typically formed over the substrate surface prior to ion implantation. The mask is formed by coating the substrate with a photoresist layer which is then exposed to activating radiation through a patterned photomask and developed to form a resist pattern. The resist pattern includes openings exposing the underlying substrate, the openings corresponding to regions of the semiconductor substrate to be implanted and regions of the substrate underlying the resist mask being protected from implantation. Following implantation, the resist mask is stripped from the substrate and the substrate is annealed.

"As photolithography technology approaches its resolution limits, the printing of fine geometries on the substrate surface is a challenge. As a result of the extremely fine geometries required in the current generation of semiconductor devices, even small variations in the ion implantation process can adversely affect electrical properties of the formed devices. One factor detrimental to the ion implantation process is the presence of photoresist residue (scum) on regions of the substrate to be implanted following patterning of the implant mask. The presence of such resist scum can drastically impact device yield.

"US 2011/10174774 A1 discloses a method of descumming a patterned photoresist. The method includes providing a material layer to be etched covered by a patterned photoresist, performing a descumming process with a nitrogen plasma to trim the edge of the patterned photoresist, and etching the material layer using the descumming patterned photoresist as a mask. The use of a plasma descumming process such as described in this document is undesirable for use with an ion implantation mask, for example, because of the complexity of the plasma etching process and plasma-induced damage to the underlying surface.

"There is a continuing need in the art for improved ion implantation and photolithographic methods which minimize or avoid problems associated with the state of the art."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In accordance with a first aspect of the invention, methods of forming an ion implanted region in a semiconductor device are provided. The methods comprise: (a) providing a semiconductor substrate having a plurality of regions to be ion implanted; (b) forming a photoresist pattern on the semiconductor substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising a matrix polymer having acid labile groups, a photoacid generator and a solvent; coating a descumming composition over the photoresist pattern, wherein the descumming composition comprises: a matrix polymer; a free acid; and a solvent; (d) heating the coated semiconductor substrate; (e) contacting the coated semiconductor substrate with a rinsing solution to remove residual descumming composition and scum from the substrate; and (f) ion implanting the plurality of regions of the semiconductor substrate using the photoresist pattern as an implant mask.

"In accordance with a further aspect of the invention, provided are electronic devices formed by the methods described herein.


"The present invention will be described with reference to the following drawing, in which like reference numerals denote like features, and in which:

"FIG. 1A-F illustrates a process flow for forming an ion implanted region in a semiconductor device in accordance with the invention."

For additional information on this patent application, see: XU, Cheng-Bai; WU, Cheng Han; CHUNG, Dong Won; YAMAMOTO, Yoshihiro. Ion Implantation Methods. Filed December 31, 2013 and posted July 10, 2014. Patent URL:

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly

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