News Column

Researchers Submit Patent Application, "Integrated Circuit Chip with Pyramid Or Cone-Shaped Conductive Pads for Flexible C4 Connections and a Method...

July 23, 2014



Researchers Submit Patent Application, "Integrated Circuit Chip with Pyramid Or Cone-Shaped Conductive Pads for Flexible C4 Connections and a Method of Forming the Integrated Circuit Chip", for Approv

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Daubenspeck, Timothy H. (Colchester, VT); Gambino, Jeffrey P. (Westford, VT); Muzzy, Christopher D. (Burlington, VT); Sauter, Wolfgang (Richmond, VT); Sullivan, Timothy D. (Underhill, VT), filed on March 7, 2014, was made available online on July 10, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The embodiments generally relate to integrated circuit chips incorporated into electronic assemblies, such as flip-chip assemblies and stacked chip assemblies, using controlled collapsed chip connections (i.e., C4 connections). More particularly, the embodiments relate to an integrated circuit chip and a method of forming the chip with pyramid or cone-shaped conductive input/output (I/O) pads.

"As discussed in detail in U.S. Patent Application Publication No. 2009/0146316 of Jadhav et al., filed on Dec. 5, 2007, published on Jun. 11, 2009, assigned to International Business Machines Corporation of Armonk, N.Y., and incorporated herein by reference, in a flip-chip assembly an integrated circuit chip is typically mounted on a chip carrier by an array of controlled collapsed chip connections (i.e., C4 connections). The formation of such C4 connections usually involves the formation of solder balls on flat conductive pads on the active surface of an integrated circuit chip (e.g., on the same surface of the chip as the integrated circuit devices and, preferably, surrounding a core integrated circuit device region), thereby creating an array of solder bumps. Additionally, solder paste is deposited onto conductive pads within an array of openings (e.g., solder resist openings) on the surface of a chip carrier. The array of solder bumps on the integrated chip is aligned with the array of solder paste filled openings on the chip carrier. Next, the integrated circuit chip and chip carrier are pressed together and a reflow process is performed to create the solder joints (i.e., the C4 connections) that both electrically and mechanically connect the integrated circuit chip to the chip carrier. Similar C4 connections can be used to interconnect integrated circuit chips in a stacked chip assembly.

"Unfortunately, during chip operation, stress-related cracks in the C4 connections and/or the integrated circuit chip(s) can form due to a mismatch in thermal expansion (e.g., between the integrated circuit chip and the chip carrier in a flip-chip assembly and between the multiple integrated circuit chips in a stacked chip assembly). Such stress-related cracks can result in chip failure. Furthermore, such stress-related cracks can increase exponentially with the use of an organic laminate substrate as the chip carrier in a flip-chip assembly, with the use of lead-free solder material and/or with smaller pitch C4 connections (i.e., with greater C4 connection density). Therefore, there is a need in the art for an improved C4 connection that will provide greater flexibility and, thereby improved integrated circuit chip reliability."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "More particularly, disclosed are embodiments of an integrated circuit chip that can be incorporated into an electronic assembly (e.g., into a flip-chip assembly or a stacked chip assembly). Each of the embodiments comprises a semiconductor substrate having a first surface and a second surface opposite the first surface. Devices can be positioned at the first surface of the semiconductor substrate (e.g., in a core device region). Conductive pads for I/O connections can be positioned either on the first surface (e.g., surrounding the core device region) or, alternatively, on the second surface. Each conductive pad can have a same three-dimensional geometric shape with a base adjacent to the semiconductor substrate and a vertex opposite the base. For example, each conductive pad can have a pyramid or cone shape. Optionally, each conductive pad can further comprise an essentially mushroom-shaped cap atop the vertex. Each conductive pad can comprise a single layer of conductive material. Alternatively, each conductive pad can comprise multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). Each conductive pad can be left exposed to allow for subsequent connection to a corresponding solder bump on another component in the electronic assembly (e.g., on a chip carrier in the case of a flip-chip assembly or on a second integrated circuit chip in the case of a stacked chip assembly). Optionally, a solder ball can be positioned on each conductive pad covering the vertex (or cap, as applicable) so as to allow for subsequent connection to a corresponding solder paste-filled opening on another component in the electronic assembly (e.g., on a chip carrier in the case of a flip-chip assembly or on a second integrated circuit chip in the case of a stacked chip assembly).

"Also disclosed herein are embodiments of a method of forming the above-described integrated circuit chip for incorporation into an electronic assembly (e.g., into a flip-chip assembly or a stacked chip assembly). Each of the method embodiments comprises providing a semiconductor substrate having a first surface and a second surface opposite the first surface. Devices can be formed at the first surface (e.g., in a core device region). Conductive pads for I/O connections can be formed either on the first surface (e.g., surrounding the core device region) or, alternatively, on the second surface. The conductive pads can be formed such that they each have a same three-dimensional geometric shape with a base adjacent to the semiconductor substrate and a vertex opposite the base (e.g., a pyramid or cone shape). Optionally, each conductive pad can further be formed so as to have an essentially mushroom-shaped cap atop the vertex. The conductive pads can be formed, for example, so as to comprise a single layer of conductive material. Alternatively, the conductive pads can be formed so as to comprise multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). After the conductive pads are formed, they can be left exposed to allow for subsequent connection to a corresponding solder bump on another component in the electronic assembly (e.g., on a chip carrier in the case of a flip-chip assembly or on a second integrated circuit chip in the case of a stacked chip assembly). Alternatively, after the conductive pads are formed, a solder ball can be form on each conductive pad covering the vertex (or cap, as applicable) so as to allow for subsequent connection to a corresponding solder paste-filled opening on another component in the electronic assembly (e.g., on a chip carrier in the case of a flip-chip assembly or on a second integrated circuit chip in the case of a stacked chip assembly).

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawing to scale and in which:

"FIG. 1A is a cross-section diagram illustrating an embodiment of an integrated circuit chip with three-dimensional conductive pads;

"FIG. 1B is a cross-section diagram illustrating an embodiment of an integrated circuit chip with capped three-dimensional conductive pads;

"FIG. 2 is a top view diagram illustrating the integrated circuit chip of FIG. 1A or FIG. 1B;

"FIG. 3A is a cross-section diagram illustrating an exemplary pyramid-shaped conductive pad;

"FIG. 3B is a cross-section diagram illustrating an exemplary capped pyramid-shaped conductive pad;

"FIG. 4A is a cross-section diagram illustrating an exemplary cone-shaped conductive pad with a linear sidewall;

"FIG. 4B is a cross-section diagram illustrating an exemplary capped cone-shaped conductive pad with a linear sidewall;

"FIG. 5A is a cross-section diagram illustrating an exemplary cone-shaped conductive pad with a curved sidewall;

"FIG. 5B is a cross-section diagram illustrating an exemplary capped cone-shaped conductive pad with a curved sidewall;

"FIG. 6A is a cross-section diagram illustrating an exemplary single-layered three-dimensional conductive pad;

"FIG. 6B is a cross-section diagram illustrating an exemplary capped multi-layered three-dimensional conductive pad;

"FIG. 7A is a cross-section diagram illustrating a solder ball on a three-dimensional conductive pad;

"FIG. 7B is a cross-section diagram illustrating a solder ball on a capped three-dimensional conductive pad;

"FIG. 8A is a cross-section diagram illustrating a solder ball on a multi-layered three-dimensional conductive pad;

"FIG. 8B is a cross-section diagram illustrating a solder ball on a capped multi-layered three-dimensional conductive pad;

"FIG. 9 is a flow diagram illustrating a method of forming an integrated circuit chip and further forming an electronic assembly incorporating the chip;

"FIG. 10 is a top view diagram illustrating a partially completed integrated circuit chip formed according to the method of FIG. 9;

"FIG. 11 is a cross-section view diagram illustrating a partially completed integrated circuit chip formed according to the method of FIG. 9;

"FIGS. 12A and 12B are cross-section view diagrams illustrating a partially completed integrated circuit chip formed according to the method of FIG. 9;

"FIGS. 13A and 13B are cross-section view diagrams illustrating a partially completed electronic assembly formed according to the method of FIG. 9;

"FIGS. 14A and 14B are cross-section view diagrams illustrating an electronic assembly formed according to the method of FIG. 9;

"FIGS. 15A and 15B are cross-section view diagrams illustrating a partially completed integrated circuit chip formed according to the method of FIG. 9;

"FIGS. 16A and 16B are cross-section view diagrams illustrating a partially completed integrated circuit chip formed according to the method of FIG. 9;

"FIGS. 17A and 17B are cross-section view diagrams illustrating a partially completed integrated circuit chip formed according to the method of FIG. 9;

"FIGS. 18A and 18B are cross-section view diagrams illustrating a partially completed electronic assembly formed according to the method of FIG. 9; and

"FIGS. 19A and 19B are cross-section view diagrams illustrating an electronic assembly formed according to the method of FIG. 9."

For additional information on this patent application, see: Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D. Integrated Circuit Chip with Pyramid Or Cone-Shaped Conductive Pads for Flexible C4 Connections and a Method of Forming the Integrated Circuit Chip. Filed March 7, 2014 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2888&p=58&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters