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Researchers Submit Patent Application, "Image Forming Apparatus and Method of Translating Virtual Memory Address into Physical Memory Address", for...

July 23, 2014



Researchers Submit Patent Application, "Image Forming Apparatus and Method of Translating Virtual Memory Address into Physical Memory Address", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor CHO, Byoung-tae (Daejeon, KR), filed on March 7, 2014, was made available online on July 10, 2014.

The patent's assignee is SAMSUNG Electronics, Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The present general inventive concept relates to an image forming apparatus and method of translating a virtual memory address into a physical memory address, and more particularly to, an image forming apparatus and method of translating a virtual memory address into a physical memory address to improve a delay caused in a process of translating the virtual memory address into the physical memory address.

"Image forming apparatuses are apparatuses which print print data generated in a terminal, such as a computer, on a recording paper. As an example of the image forming apparatus, there is a copy machine, a printer, a facsimile, or a multi function peripheral (MFP) which includes functions and/or structures of the copy machine, the printer and the facsimile through one apparatus, or the like

"In general, since a program having a larger capacity than a capacity or size of a main memory cannot loaded in the memory using only a physical memory address space, it is impossible to execute the program having a large capacity. Since the program is sequentially executed in a processor, it is necessary that only a part of a code of the program required in the processor is present in a limited period of time or a required period of time. In this way, virtual memories have been suggested to overcome the above limitations.

"In a conventional system using a virtual address, since the virtual address is different from a physical memory address, data which is in a consecutive data space on the virtual address does not necessarily correspond to a consecutive space of the physical memory address. For example, if a spacer of 10 MB is allocated using a function, such as a malloc function, in the system using the virtual address, the space of 10 MB is consecutively arranged in the virtual address, but the space of 10 MB is consecutively or inconsecutively divided in the physical memory address in the unit of page and dispersedly arranged on the memory.

"If data programmed in the address, that is, data disposed in the space of 10 MB of the virtual address is copied to other physical memory space through an intellectual property (IP) core, the hardware IP core does not consecutively process data. If data is copied through direct memory access (DMA), the data can be copied within a consecutive stream of a physical memory address. It is because the data space is consecutive in the virtual address, but the data space is dispersed (or unaligned) in the physical memory address in the unit of page. Specifically, since the physical memory address is used in hardware, such as the IP core, within a system on chip (SoC), when the hardware IP operates, the virtual memory address has to be translated into the physical memory address to be used in a read and write process.

"Therefore, when the hardware operates, a physically consecutive space is allocated and data is copied in a corresponding area to drive the hardware or scattering/gathering DMA iteratively performed in the unit of an inconsecutive space which is dispersed in the unit of page.

"However, it is ineffective due to a dual copy that the physically consecutive space is allocated and the data is copied into the corresponding area. It may be impossible to ensure the physical consecutive space corresponding to the area according to the situation of a memory manager of an operating system and in this case, it has to wait in a stand-by state until a corresponding resource is ensured."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "The present general inventive concept provides an image forming apparatus and method of translating a virtual memory address into a physical memory address in order to improve a delay in a data read and write process of reading and writing data or a translating process of translating the virtual memory address into the physical memory address.

"Additional aspects and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.

"The foregoing and/or other aspects and utilities of the present general inventive concept may be achieved by providing an image forming apparatus including: a function unit to perform functions of the image forming apparatus, and a control unit to control the function unit to perform the functions of the image forming apparatus. The control unit includes a processor core to operate in a virtual memory address, a main memory to operate in a physical memory address and store data used in the functions of the image forming apparatus, and a plurality of input/output (I/O) logics to operate in the virtual memory address and control at least one of the functions performed by the image forming apparatus. Each of the plurality of I/O logics translates the virtual memory address into the physical memory address corresponding to the virtual memory address and accesses the main memory.

"Each of the plurality of I/O logics may include a function core to control at least one of the functions performed by the image forming apparatus, an address translation unit to translate a virtual memory address required by the function core into a physical memory address using a translation look-aside buffer (TLB), and a direct memory access (DMA) to perform access using a translated physical memory address.

"The address translation unit may return the physical memory address corresponding to the required virtual memory address within the TLB, if there is the required virtual memory address within the TLB.

"The address translation unit may search a translation table within the main memory, update the TLB according to a searching result, and return the physical memory address corresponding to the required virtual memory address within the TLB updated, if there is no virtual memory address requested within the TLB.

"Each of the plurality of I/O logics may further include an address prediction unit to predict a virtual memory address to be translated next requested by the function core according to a predetermined access pattern for image data of the image forming apparatus and update the TLB.

"The address prediction unit may predict the virtual memory address to be requested next using a preset access pattern and search whether or not the physical memory address corresponding to the predicted virtual memory address is present in the translation table, if the predetermined access pattern is present.

"The address prediction unit may determine whether or not previous prediction is accurate and change the predetermined access pattern if the previous prediction is not accurate.

"The TBL may update address information for the virtual memory address and the physical memory address corresponding to the virtual memory address according to a storage order.

"The TLB may be a cache memory.

"The I/O core may be a function core to perform at least one of an image enlargement and reduction function, an image rotation function, an image translation function, and a scan function control, a facsimile function control, and a print function control.

"The process core may translate the virtual memory address into the physical memory address corresponding to the virtual memory address and access the main memory.

"The control unit may be a system on chip (SoC) including the process core, the plurality of I/O logics, and a bus interface to connect the logics within the control unit.

"The foregoing and/or other aspects and utilities of the present general inventive concept may also be achieved by providing a method of translating a virtual memory address of an image forming apparatus into a physical memory address in an image forming apparatus, the method including: requesting an access of a main memory using a virtual memory address by an input/output (I/O) core which controls at least one of functions performed by the image forming apparatus, translating a virtual memory address requested by the I/O core into a physical memory address using a TLB, and performing an access using a translated physical memory address.

"The translating the virtual memory address into the physical memory address may include returning the physical memory address corresponding to the requested virtual memory address within the TLB if there is the virtual memory address requested within the TLB.

"The translating the virtual memory address into the physical memory address may include searching a translation table, updating the TLB according to a searching result, and returning the physical memory address corresponding to the requested virtual memory address using the updated TLB if the requested virtual memory address is not present within the TLB.

"The translating the virtual memory address into the physical memory address may further include predicting a virtual memory address to be requested next by the function core according to an access pattern for image data of the image forming apparatus.

"The predicting the virtual memory address may include predicting the virtual memory address to be requested next using a predetermined access pattern and searching whether or not a physical memory address corresponding to a predicted virtual memory address is present in the translation table, if the predetermined access pattern is present.

"The predicting the virtual memory address may include searching a translation table within the main memory and updating the TLB according to a searching result, if the predicted virtual memory address is not present within the TLB.

"The predicting the virtual memory address may include determining whether or not a previous prediction is accurate and changing the predetermined access pattern if the previous prediction is not accurate.

"The TLB may update address information for the virtual memory address and the physical memory address corresponding to the virtual memory address according to a storage order.

"The performing the access may include performing an access to the translated physical memory address through a DMA.

"The foregoing and/or other aspects and utilities of the present general inventive concept may also be achieved by providing an image forming apparatus including a function unit to perform one or more functions of the image forming apparatus, a main memory to store data corresponding to at least one of the functions of the image forming apparatus, and a control unit having a plurality of input/output logics each to translate between a virtual memory address and a physical memory address, each to control the main memory in a write and read operation of the image forming apparatus according to the translated virtual or physical memory address, and each to control the function unit in a function performing operation of the image forming apparatus according to the data of the main memory.

"The control unit may further include a process core connected to an external device to receive the data, and connected to the plurality of logics to process the data in a virtual memory address.

"The control unit may further include a process core connected to an external device to receive the data, and connected to the plurality of logics to process the data in the virtual memory address.

"The plurality of logics each may include an address translation unit to translate the virtual memory address and the physical memory address.

"The plurality of logics may include semiconductor chips formed in an integrated body or package as a system on chip.

"The plurality of logics may include semiconductor chips, at least one of the semiconductor chips may be formed in a printed circuit board, and remaining ones of the semiconductor chips may be stacked on the printed circuit board to form a system on chip or a system in package.

"The plurality of logics may include an image processing input/output logic and a scan input/output logic to correspond to the functions of the image forming apparatus.

"The main memory may be detachable attached to a housing of the image forming apparatus to be connected to the control unit.

"The control unit may further include an address prediction element to store one or more patterns of one or more virtual memory addresses such that the physical memory address corresponding to the virtual memory address is provided according to one of the stored patterns.

BRIEF DESCRIPTION OF THE DRAWINGS

"These and/or other aspects and utilities of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

"FIGS. 1A, 1B, and 1C are block diagrams illustrating an image forming apparatus according to an exemplary embodiment of the present general inventive concept;

"FIG. 2 is a view specifically illustrating a configuration of a control unit of FIG. 1A;

"FIG. 3 is a view specifically illustrating an address translation device of FIG. 2;

"FIG. 4 is a view illustrating a format of a translation look-aside table according to an exemplary embodiment of the present general inventive concept;

"FIG. 5 is a flowchart illustrating a method of translating a virtual memory address into a physical memory address according to an exemplary embodiment of the present general inventive concept;

"FIG. 6 is a flowchart illustrating a translation process of FIG. 5; and

"FIG. 7 is a flowchart illustrating a prediction process of FIG. 5."

For additional information on this patent application, see: CHO, Byoung-tae. Image Forming Apparatus and Method of Translating Virtual Memory Address into Physical Memory Address. Filed March 7, 2014 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=729&p=15&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Circuit Board, Semiconductor, SAMSUNG Electronics Co. Ltd..

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Source: Electronics Newsweekly


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