Researchers Submit Patent Application, "High Performance Isolated Vertical Bipolar Junction Transistor and Method for Forming in a Cmos Integrated Circuit", for Approval
The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "An integrated circuit may be formed using a complementary metal-oxide-semiconductor (CMOS) fabrication process, which includes n-channel metal oxide semiconductor (NMOS) transistors and p-channel metal oxide semiconductor (PMOS) transistors. CMOS offers the advantages of a relatively inexpensive fabrication process, low power dissipation circuits, and transistors that can be tightly packed and scaled. It may be desirable to incorporate a bipolar junction transistor which is electrically isolated from a substrate of the integrated circuit, which has a current gain (h.sub.fe) greater than 10, and takes up little space. It may further be desirable to integrate the isolated bipolar transistor without increasing cost or complexity of the fabrication process. Forming an isolated bipolar transistor the meets these criteria may be problematic."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
"An integrated circuit having a p-type substrate and containing an NMOS transistor, a PMOS transistor, an isolated n-channel drain extended metal oxide semiconductor (DEMOS) transistor, and an isolated vertical PNP bipolar transistor, may be formed by a process sequence which includes forming deep n-type wells in the substrate. One deep well extends under the isolated n-channel DEMOS transistor and another deep well extends under the isolated vertical PNP transistor. Shallow n-type wells are formed around the isolated n-channel DEMOS transistor and the isolated vertical PNP transistor; the shallow n-type wells and the deep n-type wells combine to isolate the isolated n-channel DEMOS transistor and the isolated vertical PNP transistor from the substrate. The shallow n-type wells also provide a body region for the NMOS transistor.
"An upper n-type layer and a lower p-type layer are formed using a common implant mask. In the isolated n-channel DEMOS transistor, the upper n-type layer provides a drain extension region, and the lower p-type layer isolates the drain extension region from the deep n-type well under the isolated n-channel DEMOS transistor. In the isolated vertical PNP transistor, the upper n-type layer provides a base, and the lower p-type layer provides a collector. A plurality of p-type diffused regions are formed which provide source and drain regions for the PMOS transistor and provide an emitter for the isolated vertical PNP transistor. A plurality of n-type diffused regions are formed which provide a source region for the isolated n-channel DEMOS transistor and provide source and drain regions for the NMOS transistor. The isolated vertical PNP transistor is thus formed advantageously without increasing fabrication cost or complexity of the integrated circuit.
"An integrated circuit having an n-type substrate and containing an NMOS transistor, a PMOS transistor, an isolated p-channel drain extended transistor, and an isolated vertical NPN bipolar transistor, may be formed by appropriate reversal of conductivity types and dopant types.
DESCRIPTION OF THE VIEWS OF THE DRAWING
"FIG. 1 is a cross section of an example integrated circuit.
"FIG. 2A through FIG. 2I are cross sections of the integrated circuit of FIG. 1, depicted in successive stages of fabrication.
"FIG. 3A and FIG. 3B are cross sections of another example integrated circuit.
"FIG. 4 is a cross section of a further example integrated circuit.
"FIG. 5 is a cross section of a further example integrated circuit."
For additional information on this patent application, see:
Keywords for this news article include: Electronics, Semiconductor,
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