The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The demand for high performance in advanced ULSI circuits requires a copper interconnect to carry high current density. This places severe challenges on copper interconnect reliability, especially concerning electromigration issues. Electromigration decreases the reliability of integrated circuits (ICs), with eventual loss of connections or failure of the circuit. Also, with increasing miniaturization, the probability of failure due to electromigration increases in very-large-scale integration (VLSI) and ultra-large-scale integration (ULSI) circuits because both the power density and the current density increase. Thus, as the structure size in ICs decreases, the practical significance of the electromigration effect increases.
"In advanced semiconductor manufacturing processes, copper has replaced aluminum as the interconnect material of choice. Despite its greater fragility in the fabrication process, copper is intrinsically less susceptible to electromigration. However, electromigration continues to be an ever present challenge to device fabrication.
"In dual damascene Cu interconnects, the via has been the weakest link for electromigration, especially for the via depletion mode, i.e., for electrons flowing from a dual damascene via upwards into a line. The common electromigration failure for this mode is void formation within the via. With the technology scaling, a void in the via needed to cause an electromigration failure becomes smaller, and consequently, the failure time becomes shorter.
"Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In an aspect of the invention, a method comprises forming a dual damascene structure in a substrate. The method further comprises reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further comprises forming a liner material on the material over or within the via of the dual damascene structure. The method further comprises filling any remaining portions of the via and a trench of the dual damascene structure with additional material.
"In an aspect of the invention, a method comprises forming a dual damascene structure in a single dielectric layer, comprising a via of a first cross section and a trench of a second cross section larger than the first cross section. The method further comprises lining the via and the trench with a liner and a seed layer. The method further comprises reflowing the seed layer such that it partially or completely fills the via. The method further comprises forming a blocking liner over the reflowed seed layer which partially or completely fills the via. The method further comprises forming additional material in the trench on the blocking liner and within any remaining portions of the via.
"In an aspect of the invention, a structure comprises a via interconnect in a dielectric material comprising a liner and a conductive material. The structure further comprises an upper wiring layer in the dielectric material and in alignment with the via interconnect. The upper wiring layer comprises a liner and the conductive material. The structure further comprises a blocking liner embedded within the conductive material over the via interconnect and below the upper wiring layer which is located such that void formation due to electromigration or stress migration is prevented in the via interconnect.
"In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the dual damascene structure with an embedded liner, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the dual damascene structure with the embedded liner. The method comprises generating a functional representation of the structural elements of the dual damascene structure with the embedded liner.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
"The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
"FIGS. 1, 2, 3, 4a, 4b, 5, and 6 show structures and respective processing steps in accordance with aspects of the present invention; and
"FIG. 7 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test."
For additional information on this patent application, see: Li, Baozhen; Yang, Chih-Chao. Dual Damascene Structure with Liner. Filed
Keywords for this news article include: Electronics, Semiconductor,
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