News Column

Researchers Submit Patent Application, "Decmos Formed with a through Gate Implant", for Approval

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Hao, Pinghai (Plano, TX); Chatterjee, Amitava (Plano, TX); Khan, Imran (Richardson, TX), filed on December 27, 2013, was made available online on July 10, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "An integrated circuit may include a low-voltage metal oxide semiconductor (MOS) transistor and a drain extended metal oxide semiconductor (DEMOS) transistor of the same polarity. Body wells and source/drain regions may be formed to provide desired performance in the low-voltage MOS transistor, such that performance of the DEMOS transistor is less than desired. Adding implants to the fabrication process to improve the DEMOS transistor may undesirably increase the fabrication cost of the integrated circuit."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.

"An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.

DESCRIPTION OF THE VIEWS OF THE DRAWING

"FIG. 1 is a cross section of an example integrated circuit.

"FIG. 2A through FIG. 2D are cross sections of the integrated circuit of FIG. 1, depicted at key stages of fabrication.

"FIG. 3 is a cross section of another example integrated circuit.

"FIG. 4A through FIG. 4C are cross sections of the integrated circuit of FIG. 3, depicted at key stages of fabrication.

"FIG. 5 is a cross section of a further example integrated circuit.

"FIG. 6A through FIG. 6C are cross sections of the integrated circuit of FIG. 5, depicted at key stages of fabrication."

For additional information on this patent application, see: Hao, Pinghai; Chatterjee, Amitava; Khan, Imran. Decmos Formed with a through Gate Implant. Filed December 27, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6292&p=126&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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