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Researchers Submit Patent Application, "Configurable-Width Memory Channels for Stacked Memory Structures", for Approval

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Chow, Alex (Palo Alto, CA); Amberg, Philip (San Jose, CA); Hopkins, II, Robert David (Foster City, CA), filed on January 2, 2013, was made available online on July 10, 2014.

The patent's assignee is Oracle International Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "This disclosure generally relates to the design of a semiconductor chip package. More specifically, this disclosure relates to a chip package in which a set of memory structures that are stacked upon a host structure in the chip package provide a configurable-width memory channel.

"In many conventional computer systems, multiple DRAM devices are arranged in parallel to provide a fixed-width data interface with a memory controller. Because limited pin and routing resources in a memory module prevent individual addressing of each memory chip, memory devices within a given rank are typically accessed in lockstep using an address provided on a shared bus. In such designs, the memory controller reads and writes data in blocks of a prescribed data word, regardless of the actual number of bytes requested by the processor.

"Unfortunately, such designs can lead to inefficient memory accesses. For example, consider an access for a commodity DRAM module that supports a 64-bit wide data bus. If a processor requests and uses only a single byte (e.g., eight bits) of data at random, the memory access is inefficient, because only one out of every eight bytes of data transferred is useful.

"Hence, what is needed are structures and techniques for accessing memory systems without the above-described problems of existing techniques."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip. Individually addressable memory chips that are each accessed via separate command and address buses facilitate a configurable-width memory channel that efficiently supports different data-access granularities.

"In some embodiments, the chip package also comprises an interposer located between the semiconductor die and the memory chips. In these embodiments, contacts on the interposer are directly connected to contacts on the semiconductor die, and contacts on each individual memory chip are each directly connected to a distinct set of contacts on the interposer such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip via the interposer. Note that the interposer may be larger than the semiconductor die, and may provide power to the memory chips.

"In some embodiments, the semiconductor die sends a memory request to a subset of the memory chips. These memory chips perform (in parallel) a memory operation in response to this memory request. During this operation, a second subset of the two or more memory chips that do not store data requested by the memory request do not receive the memory request, and remain in a standby state. Performing the memory operation in only the first subset of memory chips reduces the power used by the chip package for memory requests with a data-access granularity that is smaller than the full memory width supported by the full set of memory chips.

"In some embodiments, the semiconductor die sends a memory request to all of the memory chips. In these embodiments, all of the memory chips perform a memory operation in parallel in response to the second memory request, thereby using the full memory width supported by the full set of memory chips.

"In some embodiments, the semiconductor die simultaneously sends two distinct memory requests to different subsets of the memory chips. The first memory request is sent to a first subset of the memory chips, while the second request is sent to a second, distinct subset of the memory chips. Both subsets of memory chips simultaneously perform separate memory operations in response to the memory requests.

"In some embodiments, the memory chips are stacked upon the semiconductor die at an offset such that the pins of each memory chip are directly connected to contacts on the semiconductor die. Stacking the two or more memory chips upon the semiconductor die increases memory chip density and shortens I/O trace lengths, thereby facilitating individually addressing each of the memory chips.

"In some embodiments, the memory chips are stacked vertically on top of the semiconductor die and are connected to the semiconductor die using through-silicon vias.

"In some embodiments, the chip package includes a customized memory controller that facilitates accessing data with variable granularities from the memory chips. This customized memory controller can determine when only a subset of the memory chips are needed for a given memory access and, if so, issue requests to only that subset of the memory chips. Furthermore, the customized memory controller can also determine when multiple memory requests access different subsets of the memory chips and, if so, issue parallel requests to those different subsets.

"In some embodiments, a compiler is configured to generate memory instructions that store data into the memory chips in a layout that takes advantage of the configurable-width memory channel to reduce the power usage of the chip package during operation.

"In some embodiments, an application is configured to perform memory operations that store data into the memory chips in a layout that takes advantage of the configurable-width memory channel to reduce the power usage of the chip package during operation.

BRIEF DESCRIPTION OF THE FIGURES

"FIG. 1 illustrates the organization of a DRAM memory chip in accordance with an embodiment.

"FIG. 2A illustrates a non-error-correcting code dual in-line memory module (DIMM) in accordance with an embodiment.

"FIG. 2B illustrates bus routings for an exemplary non-error-correcting code DIMM in accordance with an embodiment.

"FIG. 3A illustrates a set of stacked memory chips that are stacked at an offset such that the pins of each memory chip are directly exposed to an underlying logic chip or substrate in accordance with an embodiment.

"FIG. 3B illustrates a set of stacked memory chips that are stacked upon an interposer in accordance with an embodiment.

"FIG. 4 illustrates an exemplary conceptual memory stack that is assembled using DRAM memory components in accordance with an embodiment.

"FIG. 5 presents a flow chart that illustrates the process of performing a configurable-width memory access in accordance with an embodiment.

"FIG. 6 illustrates an exemplary organization in which data is striped across a stacked memory system with eight .times.8 DRAM memory chips in accordance with an embodiment.

"FIG. 7 illustrates several examples of memory layouts for a stacked memory system that are advantageous to specific workloads and applications in accordance with an embodiment.

"FIG. 8 illustrates a computing environment in accordance with an embodiment.

"Table 1 illustrates the pin-out of an unbuffered DIMM in accordance with an embodiment."

For additional information on this patent application, see: Chow, Alex; Amberg, Philip; Hopkins, II, Robert David. Configurable-Width Memory Channels for Stacked Memory Structures. Filed January 2, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4570&p=92&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Electronics, Semiconductor, Oracle International Corporation.

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Source: Electronics Newsweekly


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