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Patent Issued for Vertical Channel Memory and Manufacturing Method Thereof and Operating Method Using the Same

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Hsu, Tzu-Hsuan (Chiai County, TW); Lue, Hang-Ting (Hsinchu, TW), filed on April 17, 2007, was published online on July 8, 2014.

The assignee for this patent, patent number 8772858, is Macronix International Co., Ltd. (Hsinchu, TW).

Reporters obtained the following quote from the background information supplied by the inventors: "The invention relates in general to a vertical channel memory, to a manufacturing method thereof therefor and to an operating method using the same. More particularly the invention relates to a vertical channel memory with high scalability, to a manufacturing method therefor and to an operating method using the same.

"Along with the advance in manufacturing technology for semiconductor devices, the resolution of current semiconductor elements has reached nano levels. Take the memory for example, the length of the gate and the element pitch are further reduced. With sizes near the resolution limits of lithography, the manufactured transistor element still has the problems of electrostatic discharge (ESD), leakage, and reduction in electron mobility, and is apt to short channel effect and drain induced barrier lowering (DIBL) effect. Therefore, the double-gate vertical channel transistor and the tri-gate vertical channel transistor capable of providing higher packing density, better carrier transport and device scalability, such as fin field effect transistor (FinFET), have become transistor structures with great potential.

"The FinFET has a vertical channel, and can form channels on two vertical surfaces and control the connection of current by double-gate or tri-gate structures, hence having better efficiency than conventional planar channel transistors.

"The manufacturing of FinFET elements with high resolution still requires expensive and advanced manufacturing processes by photolithography or E-beam. However, the throughput of these advanced manufacturing processes is difficult to increase and is disadvantageous to large-scale production. One of the present manufacturing methods is etching a channel first and then the line width of the channel is reduced by oxidation. However, the element formed according to such method has poor uniformity and the quality is difficult to control."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The invention is directed to a vertical channel memory, a manufacturing method therefor and an operating method using the same. A vertical channel transistor structure whose channel width ranges between 10 nm.about.60 nm is manufactured without changing the pitch of the element formed by exposure. The invention effectively increases the driving current during programming or reading without incurring short channel effect or DIBL effect. The FinFET transistor formed thereby has small dimension, hence increasing memory density significantly. Furthermore, the invention provides an SONOS memory with band gap engineered structure, so-called BE-SONOS memory. Compared with the conventional vertical channel memory with SONOS structure, the vertical channel memory with BE-SONOS structure has faster operating speed and wider operating window. The vertical channel memory with BE-SONOS structure can locally trap charge and can enlarge the range of the operating window to achieve multi-level cell MLC memory.

"According to a first aspect of the present invention, a vertical channel memory including a substrate, a channel, a cap layer, a charge storage layer, a first terminal and a second terminal is provided. The channel protrudes from the substrate and has a top surface and two vertical surfaces. The cap layer disposed on the channel substantially has the same width with the channel. The charge storage layer is disposed on the cap layer and the two vertical surfaces of the channel. The gate straddling the charge storage layer is positioned at the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

"According to a second aspect of the present invention, a manufacturing method of vertical channel memory is provided. First, a substrate is provided. Next, a first nitride layer is formed on the substrate. Then, the first nitride layer is etched to form a first patterned nitride layer. Next, the first patterned nitride layer is trimmed to form a second patterned nitride layer. Then, the substrate is etched to form at least a channel protruding from the substrate. Next, a thick oxide layer is formed on a top surface of the substrate. Then, an oxide-nitride-oxide (ONO) layer is formed on the two vertical surfaces of the channel. Next, a gate material layer is formed on the ONO layer. Then, the gate material layer is etched to form at least a gate, wherein the gate is positioned on the two vertical surfaces of the channel such that fin gate is formed on a protruding fin structure of the vertical channel memory. Next, ions are injected on the two sides of the channel opposite to the gate to form a first terminal and a second terminal.

"According to a third aspect of the present invention, a vertical channel memory including the substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel protrudes from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling the multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

"According to a fourth aspect of the present invention, a manufacturing method of vertical channel memory is provided. The manufacturing method includes following steps. First, a substrate is provided. Next, a first nitride layer is formed on the substrate. Then, the first nitride layer is etched to form a first patterned nitride layer. Next, the first patterned nitride layer is trimmed to form a second patterned nitride layer. Then, the substrate is etched to form at least a channel protruding from the substrate, wherein the channel has a top surface and two vertical surfaces. Next, a thick oxide layer is formed on the top surface of the substrate. Then, an ONONO layer is formed on the two vertical surfaces of the channel. Then, a gate material layer is formed on the ONONO layer. Next, the gate material layer is etched to form at least a gate positioned above the two vertical surfaces of the channel. Then, ions are injected on the two sides of the channel opposite to the gate so as to form a first terminal and a second terminal.

"According to a fifth aspect of the present invention, an operating method of memory is provided. The operating method is used in a vertical channel memory. The vertical channel memory has a channel protruding from a substrate. The channel has a top surface and two vertical surfaces. The ONONO layer is disposed on the channel. The gate straddling ONONO layer is positioned above the two vertical surfaces of the channel. A first terminal and a second terminal are respectively opposite to the gate and positioned at the two sides of the channel. The operating method includes the following steps. First, a first bias-voltage is applied to the gate to program the vertical channel memory. Next, a second bias-voltage whose polarity is opposite to that of the first bias-voltage is applied to the gate so as to erase the vertical channel memory.

"The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings."

For more information, see this patent: Hsu, Tzu-Hsuan; Lue, Hang-Ting. Vertical Channel Memory and Manufacturing Method Thereof and Operating Method Using the Same. U.S. Patent Number 8772858, filed April 17, 2007, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772858.PN.&OS=PN/8772858RS=PN/8772858

Keywords for this news article include: Electronics, Semiconductor, Macronix International Co. Ltd..

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Source: Electronics Newsweekly


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