The patent's assignee for patent number 8775994 is
News editors obtained the following quote from the background information supplied by the inventors: "In modern integrated circuits (ICs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are being constructed at sizes close to their physical limits. The scaling of these devices in order to accommodate the ever increasing demand for faster and more complex Integrated Circuits has resulted in increasingly high electric fields within these MOSFETs. These increased electric fields can contribute to reliability problems for the long term operation of these devices.
"One such mechanism that causes reliability problem is hot carrier injection (HCI). Hot carrier injection is a phenomenon in solid-state electronic devices where an electron or a 'hole' gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. The term 'hot' refers to the effective temperature used to model carrier velocity, not to the overall temperature of the device. Since the charge carriers can become trapped in the gate dielectric of a MOS transistor, the switching characteristics of the transistor can be permanently changed.
"Another mechanism that causes reliability problems seen in integrated circuits results from time-dependent gate dielectric breakdown (or time dependent dielectric breakdown--TDDB). Time dependent dielectric breakdown is a failure mechanism in MOSFETs that occurs when the gate dielectric breaks down as a result of long-time application of relatively low electric field (as opposite to immediate breakdown, which is caused by strong electric field). The breakdown is caused by formation of a conducting path through the gate dielectric to substrate due to electron tunneling current. This typically occurs when MOSFETs are operated close to or beyond their specified operating voltages. Yet another mechanism that can cause reliability problems is bias temperature instability (BTI) (a.k.a., negative bias temperature instability--NBTI)."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "An embodiment of the invention may therefore comprise a method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. And, based on the total MOS transistor gate area, calculating a time dependent dielectric breakdown lifetime (TDDB).
"An embodiment of the invention may therefore further comprise a method for checking for reliability problems of an integrated circuit that includes determining a first total MOS transistor gate area for a first gate dielectric thickness for substantially an entire integrated circuit. An expected lifetime of a first MOS transistor is calculated based on this first total MOS transistor gate area, V.sub.gb, a temperature parameter, the length of the channel of the first MOS transistor, a calculated gate-to-source voltage (V.sub.gs), and, a calculated drain-to-source voltage (V.sub.ds). An expected lifetime of the integrated circuit is calculated based on the shortest lifetime from the plurality of transistors contained in the integrated circuit calculated as above or by integrating the results of individual transistors using techniques in the literature."
For additional information on this patent, see: Weir, Bonnie E.; Banoo, Kausar. Using Entire Area of Chip in TDDB Checking. U.S. Patent Number 8775994, filed
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