The patent's inventors are Teman, Adam (Ramat Gan, IL); Pergament, Lidor (Tel Aviv-Yafo, IL); Cohen, Omer (Rishon LeZiyyon, IL); Fish, Alexander (Tel Mond, IL).
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Embodiments of the present invention relate to semiconductor memory devices, and more particularly to an ultra low power consumption random access memory cell that is designed for minimal leakage operation.
"The ongoing demand for ultra low power consumption integrated circuits lead to sub-threshold and near-threshold operation of digital circuits. These approaches utilize very low supply voltages for digital circuit operation, decreasing the dynamic power quadratically, and sufficiently reducing leakage currents. As static power is often the primary factor in a system's power consumption, especially for low to medium performance systems, supply voltage scaling for minimization of leakage currents is essential. Optimal power-delay studies show that the
"Low voltage operation of static Complementary Metal Oxide Semiconductor (CMOS) logic is quite straightforward, as its non-ratioed structure generally achieves robust operation under process variations and device mismatch. However, when ratioed designs are put under extreme conditions, maintaining functionality becomes challenging. Global variations change the drive strength ratio between n-channel MOS (nMOS) and p-channel MOS (pMOS) devices, often overcoming the sizing considerations taken into account when designing the circuits. Local mismatch brings an even tougher challenge, as the drive strength ratios between similar devices can be affected, and symmetrically designed circuits can easily lose functionality. At sub and near-threshold supply voltages, these fluctuations in drive strength are often more substantial than the effects of sizing and mobility. Thus a circuit that is fully operational at the typical process corner or when all devices are slow or fast, may not function at the fast nMOS/slow pMOS (aka FS) or fast pMOS/slow nMOS (aka SF) corners. Even if functionality is achieved at all process corners, local mismatch can cause failure.
"FIG. 1 shows a circuit diagram of a standard six-transistor static
"FIG. 2 shows a circuit diagram of a standard eight-transistor static
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "One aspect of the present invention provides a memory cell with an internal supply feedback loop which significantly reduces leakage currents flowing through the latch, compared with standard eight-transistor static
"Additional, and/or other aspects and/or advantages of the embodiments of the present invention are set forth in the detailed description which follows; possibly inferable from the detailed description; and/or learnable by practice of the embodiments of the present invention."
For the URL and additional information on this patent, see: Teman, Adam; Pergament, Lidor; Cohen, Omer; Fish, Alexander. Ultra
Keywords for this news article include: Electronics, Semiconductor, Digital Circuits, Ben-Gurion University of the
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