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Patent Issued for Ultra Low Power Memory Cell with a Supply Feedback Loop Configured for Minimal Leakage Operation

July 23, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- Ben-Gurion University of the Negev Research and Development Authority (Beer-Sheva, IL) has been issued patent number 8773895, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Teman, Adam (Ramat Gan, IL); Pergament, Lidor (Tel Aviv-Yafo, IL); Cohen, Omer (Rishon LeZiyyon, IL); Fish, Alexander (Tel Mond, IL).

This patent was filed on February 26, 2013 and was published online on July 8, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Embodiments of the present invention relate to semiconductor memory devices, and more particularly to an ultra low power consumption random access memory cell that is designed for minimal leakage operation.

"The ongoing demand for ultra low power consumption integrated circuits lead to sub-threshold and near-threshold operation of digital circuits. These approaches utilize very low supply voltages for digital circuit operation, decreasing the dynamic power quadratically, and sufficiently reducing leakage currents. As static power is often the primary factor in a system's power consumption, especially for low to medium performance systems, supply voltage scaling for minimization of leakage currents is essential. Optimal power-delay studies show that the Minimum Energy Point (MEP) is found in the sub-threshold region, where ultra-low power figures are achieved, at the expense of orders-of-magnitude loss in performance.

"Low voltage operation of static Complementary Metal Oxide Semiconductor (CMOS) logic is quite straightforward, as its non-ratioed structure generally achieves robust operation under process variations and device mismatch. However, when ratioed designs are put under extreme conditions, maintaining functionality becomes challenging. Global variations change the drive strength ratio between n-channel MOS (nMOS) and p-channel MOS (pMOS) devices, often overcoming the sizing considerations taken into account when designing the circuits. Local mismatch brings an even tougher challenge, as the drive strength ratios between similar devices can be affected, and symmetrically designed circuits can easily lose functionality. At sub and near-threshold supply voltages, these fluctuations in drive strength are often more substantial than the effects of sizing and mobility. Thus a circuit that is fully operational at the typical process corner or when all devices are slow or fast, may not function at the fast nMOS/slow pMOS (aka FS) or fast pMOS/slow nMOS (aka SF) corners. Even if functionality is achieved at all process corners, local mismatch can cause failure.

"FIG. 1 shows a circuit diagram of a standard six-transistor static SRAM cell 100 (write and read circuitry not shown here) according to the prior art. SRAM cell 100 is constructed of a pair of cross coupled static CMOS inverters, which are non-ratioed and therefore operational under process variations at very low supply voltages. However, accessing the data stored in the cell is a ratioed process, including a contention between a pull up and a pull down network in both read and write operations. During nominal strong inversion operation, sizing considerations are incorporated to ensure writeability and readability. However, at low voltages, process variations and mismatch cause a loss of functionality. Both theoretical and measured analysis show that standard SRAM blocks are limited to operating voltages of no lower than 700 mV.

"FIG. 2 shows a circuit diagram of a standard eight-transistor static SRAM cell 200 according to the prior art. Standard eight-transistor static SRAM cell 200 includes the aforementioned six-transistor circuitry, a two port write configuration that includes two write circuitry (each for writing a logic `0` to either node Q or node QB via nMOS access devices) and a read circuitry with a decoupled read out path. Standard eight-transistor static SRAM cell 200 features read margins equivalent to its hold margins, however its write margins maintain the aforementioned 700 mV supply limitation."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "One aspect of the present invention provides a memory cell with an internal supply feedback loop which significantly reduces leakage currents flowing through the latch, compared with standard eight-transistor static SRAM cell 200. The memory cell includes: a latch having a supply node, a ground node, a storage node Q, and a storage node QB; a gating device having a control node and further connected to a voltage supply and to the supply node of the latch; and a feedback loop connecting storage node QB with the control node of the gating device, wherein the ground node of the latch is connected to ground and wherein storage node Q and the storage node QB are connected each to a different write circuitry. Due to the aforementioned asymmetric topology, the writing of logic '1' and the writing of logic '0' into the memory cell are carried out differently. In contrary to a standard SRAM cell, in the hold states, only the QB storage node presents a valid value of stored data. This is because at steady state, both after writing logic '0' and after writing logic '1', the feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch (but it is stable all the same). By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states characterizing the operation of static memory cells are eliminated altogether in the memory cell provided herein.

"Additional, and/or other aspects and/or advantages of the embodiments of the present invention are set forth in the detailed description which follows; possibly inferable from the detailed description; and/or learnable by practice of the embodiments of the present invention."

For the URL and additional information on this patent, see: Teman, Adam; Pergament, Lidor; Cohen, Omer; Fish, Alexander. Ultra Low Power Memory Cell with a Supply Feedback Loop Configured for Minimal Leakage Operation. U.S. Patent Number 8773895, filed February 26, 2013, and published online on July 8, 2014. Patent URL:

Keywords for this news article include: Electronics, Semiconductor, Digital Circuits, Ben-Gurion University of the Negev Research and Development Authority.

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Source: Electronics Newsweekly

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