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Patent Issued for Storing Data in Parallel in a Flash Storage Device Using on Chip Page Shifting between Planes

July 22, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Sprouse, Steven (San Jose, CA); Gorobets, Sergey Anatolievich (Edinburgh, GB), filed on December 30, 2011, was published online on July 8, 2014.

The assignee for this patent, patent number 8775722, is SanDisk Technologies Inc. (Plano, TX).

Reporters obtained the following quote from the background information supplied by the inventors: "Non-volatile memory systems, such as flash memory devices, have been widely adopted for use in consumer products. Flash memory devices may be found in different forms, for example in the form of a portable memory card that can be carried between host devices or as a solid state disk (SSD) embedded in a host device. When writing data to a conventional flash memory device, a host typically writes data to, and reads data from, addresses within a logical address space of the memory system.

"The flash memory device includes an array of floating-gate memory cells and a system controller. The controller manages communication with the host system and operation of the memory cell array in order to store and retrieve user data. In order to increase the degree of parallelism during programming user data into the memory array and reading user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into the planes, or each plane may be formed from a separate one or more flash memory chips.

"The memory cells of the flash memory device can be grouped together into pages and blocks. The page is the unit of data programming and reading within a block, containing the minimum amount of data that are programmed or read at one time. However, in order to increase the memory system operational parallelism, such pages within two or more blocks may be logically linked into metapages. A metapage may be formed of one physical page from multiple blocks. So that, the metapage, for example, may include the page in each of the multiple blocks but the pages of a metapage need not necessarily have the same relative position within each of the blocks. A metapage is the maximum unit of programming.

"The block is composed of multiple pages with the block being the smallest grouping that is simultaneously erasable. To efficiently manage the memory, blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each plane. Use of the metablock is described in U.S. Pat. No. 6,763,424, which is hereby incorporated by reference in its entirety, for all purposes. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all blocks of a metablock are erased together. The smallest metablock size may be a single physical block.

"Metablock sizes are typically kept smaller in order to comply with various standards. However, a small metablock size reduces the number of planes that can be operated in parallel, thereby increasing the time in which to program the flash memory device. Thus, a need exists to reconcile these issues."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Methods and systems are disclosed herein for storing data in a memory device.

"According to a first aspect, a method for storing data in a flash storage device is provided. The method is in a flash storage device having a controller and a memory in communication with the controller, the memory including a plurality of planes, with each of the planes having a sequence of pages. The method includes: receiving data; iteratively writing portions of the data in parallel into a page in each of the plurality of planes; reading the pages in each of the planes, with at least some of the pages read in parallel being in a different respective page of the sequence of pages in the respective plane; determining, for at least one of the pages read, whether to shift pages from an initial plane to a different one of the planes; and storing the data in the memory based on the determined shift, wherein the determined shift and the storage of the data result in a sequential ordering of data within the numbered sequence of pages in at least one of the planes. One example is a memory device that includes N number of planes. The iterative writing includes: writing the first 'N' pages of data in a first sequence across the 'N' number of planes; and using plane interleaving to write subsequent pages of data in a sequence across the 'N' number of planes that is different from the first sequence. After iteratively writing the pages of data, the data is read (either in parallel or sequentially) so that a page is read from each of the plurality of planes in a different one of the sequence of pages. After which, it is determined whether to shift the pages or perform a page swap prior to saving the pages into another section of memory. For example, the data may be read to an XDL register (or series of registers). The XDL register may then perform page swaps if necessary prior to saving the pages in multi-level cell memory.

"According to a second aspect, a flash memory device configured to store data is provided. The flash memory includes: a memory that includes a plurality of planes, each of the planes having a sequence of pages; and a controller in communication with the memory. The controller is configured to: receive data; iteratively write portions of the data in parallel into a page in each of the plurality of planes; read the pages in each of the planes, at least some of the pages read in parallel being in a different respective page of the sequence of pages in the respective plane; determine, for at least one of the pages read in parallel, whether to shift pages from an initial plane to a different one of the planes; and store the data in the memory based on the determined shift, wherein the determined shift and the storage of the data result in a sequential ordering of data within the numbered sequence of pages in at least one of the planes.

"Other features and advantages will become apparent upon review of the following drawings, detailed description and claims. Additionally, other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. The embodiments will now be described with reference to the attached drawings."

For more information, see this patent: Sprouse, Steven; Gorobets, Sergey Anatolievich. Storing Data in Parallel in a Flash Storage Device Using on Chip Page Shifting between Planes. U.S. Patent Number 8775722, filed December 30, 2011, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8775722.PN.&OS=PN/8775722RS=PN/8775722

Keywords for this news article include: SanDisk Technologies Inc..

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Source: Journal of Technology


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