The patent's assignee for patent number 8775999 is
News editors obtained the following quote from the background information supplied by the inventors: "In an application-specific integrated chip (ASIC) design flow, standard cells are placed randomly by an automatic placement tool. It is essential for the standard cell designers to verify that the cells can be placed adjacent to any other standard cells in the library without causing design rule violations. Design rules are parameters provided by semiconductor manufacturers that enable the circuit designer to verify the correctness of a mask set. The basic design rules include a width rule that specifies the minimum width of any shape in the design and a spacing rule that specifies the minimum distance between any two adjacent objects, among others. Violations of the design rules usually occur at the cell boundaries because of insufficient distance of the layers such as metal, poly, or diffusion from the boundary. Such violations represent the so-called `adjacent effect` of neighboring standard cells. One method to check for safe placement of standard cells consists of abutting each standard cell in the library with all other standard cells in every possible orientation. However, present implementations of this exhaustive method require significant amounts of time and resources in terms of processing overhead and disk space. Such current systems are also generally not compatible with double-height or multiple-height cells, and do not provide exhaustive coverage with respect to random placement of standard cells, or exhaustive coverage of randomly selected standard cells. Furthermore, if a design fault is discovered with respect to a standard cell during the design layout process, the original design itself must be changed, thus imposing significant costs to the design process.
"FIG. 1 illustrates a process of designing an integrated circuit using standard cells under typical present methods. As shown in diagram 100, the physical design comprising a placement process 102 and routing process 104 of an integrated circuit (e.g., an ASIC) is made using standard cells provided by a standard cell library 108. Depending on the technology and/or the manufacturing processes of the IC, such a library may include any number of standard cells, such as between 200 to 400 or more standard cells. An original physical design undergoes the two major steps of placement and routing. The placement process 102 is performed by a computer-aided design (CAD) layout tool (placer) to place the standard cells in a layout. The layout is provided to another CAD layout tool (router) that performs a routing process 104 to route the wires that are used to connect the terminals of the placed standard cells. In general, standard cells are placed randomly by the placer, so a designer does not have total control over device placement. The layout from the router is checked against the design rules 106 to ensure that the design rule parameters are met. If the layout passes the design rule check (DRC) process, it passes to circuit tapeout process 110 and other production steps. If, however, the layout fails any of the design rules, the layout must be fixed. Failure of the design rules may be due to routing problems or placement problems. If the failure is related to routing, the routing process 104 is redone, which is often a relatively fast operation. If the failure is due to placement however, the placement process 102 will need to redone, which can be a much more significant task. If the failure is due to placement problems and is caused by the adjacent effect of the standard cells, the problem is usually pervasive in the entire layout. When a pervasive placement process occurs, the standard cells need to be redesigned and re-characterized. This requires the designer to repeat (in one or more iterations) the synthesis and physical design steps associated with the standard cell definitions, which can obviously add significant delay and expense to the overall design process.
"The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Some embodiments are directed to a method for deriving all permutations of a layout of standard cells in the design of an integrated circuit device, with the method comprising iteratively placing of the standard cells adjacent to each side and corner of itself and each of the other standard cells to produce an interim test layout comprising a first number of cell pair permutations, and reducing the first number of cell pair permutations by identifying illegal or redundant left-right and top-bottom boundaries and removing any cell pair permutations using the illegal or redundant boundaries to generate a final test layout comprising a second number of cell pair permutations.
"Some embodiments are directed to a method for validating standard cells stored in a standard cell library and for use in the design of an integrated circuit device, with the method comprising identifying a target cell of the standard cell library and one or more test cells of the standard cell library, defining one or more orientations of the target cell with respect to an x axis and y axis of the standard cell, placing (for each orientation of the one or more orientations of the target cell) the target cell adjacent to itself and each of the one or more test cells to generate a plurality of cell pair permutations, reducing the number of placements by identifying illegal or redundant left-right and top-bottom boundaries and removing any cell pair permutations using the illegal or redundant boundaries to generate a final test layout for the target cell, and performing a design rule check on the final test cell layout to flag a possible problem associated with any cell pair permutation.
"Some embodiments are directed to an apparatus or system comprising one or more processing elements that perform the acts or process steps of the two methods described above."
For additional information on this patent, see: Chueh, Juang-Ying; Tung, Charles. Standard Cell Placement Method to Exercise Placement Permutations of
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