The patent's inventors are Lee, Hwa-seok (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Embodiments of the inventive concept relate generally to electronic memory technologies. More particularly, embodiments of the inventive concept relate to semiconductor memory devices and methods of performing read and verification operations in the semiconductor memory devices.
"Recent years have been marked by a continuing increase in the demand for semiconductor memory devices. Along with this demand, there has also been a demand for improved performance and increased storage capacity of the semiconductor memory devices.
"Two of the primary ways of improving the performance and storage capacity of semiconductor memory devices are increasing their operating speeds, and increasing their integration densities. Increasing these characteristics, however, can require improvements in the precision of their operations because devices that are faster and smaller tend to be more sensitive to minor variations in operating conditions such as timing, voltages, and so on. As a result, new techniques are continually required to ensure the reliability of next generation semiconductor memory devices."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "According to one embodiment of the inventive concept, a semiconductor memory device comprises a memory cell array configured to store data, a sensing unit configured to perform a reading operation on data stored in the memory cell array by sensing a corresponding bitline through a plurality of reading steps in response to a single reading command, and a sensing time controller configured to generate a control signal to variably control a reading time taken by each reading step performed by the sensing unit.
"According to another embodiment of the inventive concept, a semiconductor memory system comprises a semiconductor memory device comprising a memory cell array configured to store data, a sensing unit configured to perform a reading operation of data stored in the memory cell array by sensing a corresponding bitline through a plurality of reading steps according to a single reading command, and a sensing time controller configured to generate a control signal to control a reading time taken by each reading step of the sensing unit to vary between the different reading steps.
"According to still another embodiment of the inventive concept, a nonvolatile semiconductor device comprises a memory cell array, a sensing unit configured to receive a reading command to initiate a reading operation comprising a plurality of reading steps, a sensing time controller configured to receive a reading step signal indicating a number of a current reading step of the reading operation, and further configured to generate a control signal to variably control a timing of the current reading step. The reading time taken by the current reading step comprises a discharging time taken to discharge bitlines of the memory cell array, a precharging time taken to precharge the discharged bitlines among the precharged bitlines, a developing time taken to develop a voltage of the corresponding bitline, or a latch time taken to latch the developed bitline voltage.
"These and other embodiments can be used to improve the reliability of read data while performing read and verify operations at high speeds."
For the URL and additional information on this patent, see: Lee, Hwa-seok; Kim, Bo-geun. Semiconductor Memory Device and Related Methods for Performing Read and Verification Operations. U.S. Patent Number 8773914, filed
Keywords for this news article include: Semiconductor,
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