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Patent Issued for Semiconductor Device with Reduced Potential between Adjacent Floating Regions

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Terashima, Tomohide (Tokyo, JP), filed on July 13, 2011, was published online on July 8, 2014.

The assignee for this patent, patent number 8772903, is Mitsubishi Electric Corporation (Tokyo, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "Semiconductor devices provided with a structure for increasing the breakdown voltage have been known, as disclosed, e.g., in Japanese Laid-Open Patent Publication No. 2000-243978. Specifically, this publication relates to providing a highly reliable high voltage semiconductor device which does not exhibit degradation of the breakdown voltage (or withstand voltage) of its pn junction under a high temperature bias reliability test. The semiconductor device disclosed in the publication includes a p-type diffusion region and an n-type diffusion region formed on an n-type semiconductor substrate, first layer plate electrodes disposed on an oxide film between these diffusion regions, and second layer plate electrodes disposed on an interlayer insulating film on the first layer plate electrodes. Thus, these plate electrodes are arranged over the pn junction and capacitively coupled to one another, thereby increasing the breakdown voltage of the pn junction.

"Other prior art includes Japanese Laid-Open Patent Publication No. H06-216231.

"Incidentally, the present inventor has intensively studied the configurations of semiconductor devices, such as ICs (integrated circuits), having a plurality of different potential regions therein in order to increase the breakdown voltage of the devices, and found the following:

"FIG. 10 is a cross-sectional side view of a semiconductor device, and will be used to describe the problem sought to be solved by the present invention. The semiconductor device shown in FIG. 10 is provided with a substrate 1, an insulating layer 20, and a plurality of regions 3 of different potentials. The semiconductor substrate 1 is a so-called SOI (silicon on insulator) wafer including a semiconductor material layer 10 and the insulating layer 20, which is an SiO.sub.2 insulating film. The regions 3 are island regions on this SOI wafer which are separated and isolated from each other. In the following description, the plurality of regions 3 are denoted by reference numerals 3(0), 3(1), . . . , 3(k), 3(k+1), . . . 3(n), and 3(n+1) to distinguish them, where k and n are positive integers. (That is, there are n+2 number of regions 3.)

"These different potential regions 3(0) to 3(n+1) are separated and isolated by trenches. The n intermediate regions 3(1) to 3(n) disposed between the rightmost region 3(0) and the leftmost region 3(n+1), as viewed in FIG. 10, are floating regions which are in a floating state and are of substantially the same configuration. These floating regions 3(1) to 3(n) are also hereinafter referred to collectively as the floating regions 3(k) for convenience of explanation, that is, k is a positive integer from 1 to n. As shown in FIG. 10, a potential of 0 (V) is applied to the rightmost region 3(0) and a potential of V.sub.n+1(V) is applied to the leftmost region 3(n+1). The voltage (or potential difference) between the rightmost and leftmost regions 3(0) and 3(n+1) is capacitively divided so that the regions 3(1) to 3(n) are at different potentials. The potentials of the regions 3(1) to 3(n) are designated by V.sub.1, V.sub.2, . . . , V.sub.k, . . . , V.sub.n, respectively. Thus, as shown in FIG. 10, the high voltage V.sub.n+1 between the regions 3(0) and 3(n+1) is capacitively divided by the capacitances formed between the regions 3(0) to 3(n+1), thereby increasing the overall breakdown voltage of the device.

"However, the present inventor has found that the above breakdown voltage increasing method using a capacitive divider has the following disadvantage:

"FIG. 11 is an equivalent circuit diagram of the structure of FIG. 10. Let a.sub.k represent the capacitance between the region 3(k) and the substrate, and b.sub.k represent the capacitance between the region 3(k) and the region 3(k+1), where k is 0 or a positive integer. Then the following relations hold:

".function..times..times..times..times..function..function..times..functio- n..times..times..times. ##EQU00001##

"If a.sub.k and b.sub.k are constant with respect to the value of k and are represented by a and b respectively, then the following equations hold

".alpha..times..times..times..beta..times..times..times..alpha..beta..time- s..alpha..times..times..beta..beta..times..times..alpha..times..alpha..bet- a..times..times..times..times..times..times..times..function..alpha..beta.- .alpha..beta. ##EQU00002##

"Since .alpha.>1 and .beta.

"Thus, the breakdown voltage increasing method described above with reference to FIG. 10, which uses a capacitive divider made up of successively arranged floating regions 3(k), is disadvantageous in that the voltages between adjacent floating regions 3(k) are not equal and increase with decreasing distance from the high potential end of the device. As a result, different voltage stresses are applied to the separation trenches, resulting in a reduced overall breakdown voltage and reduced reliability.

"The present invention has been made to solve the above problems. It is, therefore, an object of the present invention to provide a semiconductor device wherein the differences between the voltages between a plurality of adjacent floating regions are reduced."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "According to a first aspect of the present invention, a semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion forms an external capacitance in parallel with either the capacitance of the insulating region between the first floating region and the island region of the predetermined potential, or the capacitance of the insulating region between each adjacent pair of one or more of the plurality of floating regions, or both, the one or more floating regions including the first floating region.

"According to a second aspect of the present invention, a semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion extends either along and above the semiconductor substrate, or along a side of the row of the plurality of floating regions on the surface of the semiconductor substrate, or both, so that the capacitance forming portion is capacitively coupled to one or more of the plurality of floating regions, the one or more floating regions including the first floating region.

"In accordance with the first aspect of the present invention there is provided a semiconductor device in which a capacitance forming portion provides capacitances to reduce the differences between the voltages between adjacent floating regions.

"In accordance with the second aspect of the present invention there is provided another semiconductor device in which a capacitance forming portion provides capacitances to reduce the differences between the voltages between adjacent floating regions."

For more information, see this patent: Terashima, Tomohide. Semiconductor Device with Reduced Potential between Adjacent Floating Regions. U.S. Patent Number 8772903, filed July 13, 2011, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772903.PN.&OS=PN/8772903RS=PN/8772903

Keywords for this news article include: Electronics, High Voltage, Semiconductor, Mitsubishi Electric Corporation.

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Source: Electronics Newsweekly


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