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Patent Issued for Semiconductor Device Including Inner Interconnection Structure Able to Conduct Signals Or Voltages in the Semiconductor Chip with...

July 23, 2014



Patent Issued for Semiconductor Device Including Inner Interconnection Structure Able to Conduct Signals Or Voltages in the Semiconductor Chip with Vertical Connection Vias and Horizontal Buried Condu

By a News Reporter-Staff News Editor at Electronics Newsweekly -- SK Hynix Inc. (Gyeonggi-do, KR) has been issued patent number 8772937, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Seo, Hyun Chul (Seoul, KR); Lee, Seung Yeop (Seoul, KR).

This patent was filed on June 17, 2011 and was published online on July 8, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Exemplary embodiments of the present invention relate to semiconductor technologies, and more particularly, to a semiconductor device including an inner interconnection structure.

"A semiconductor device package requires semiconductor chips to be mounted at a high density in a small area. Therefore, what is being developed is a technology for forming a three-dimensional stack package by contacting semiconductor chips using a through silicon via (TSV) structure. Because the TSV is formed to pierce a semiconductor chip, the TSV structure can reduce an electrical signal transmission path more effectively than a wire bonding structure. Thus, the TSV structure is expected to be advantageous to high-speed operation devices.

"Because the TSV is introduced to pierce the semiconductor chip, the TSV is located in a restricted region on the surface of the semiconductor chip. Although the TSV cannot be disposed in an active region of the semiconductor chip in which circuit elements are integrated, the TSV may be located in an edge region of the semiconductor chip or in a center region of the semiconductor chip in which a scribe lane region is located. Thus, the exposure location of a TSV exposed as a connection terminal on the rear surface of the semiconductor chip is restricted within the restricted region.

"Solder balls may be used when mounting a semiconductor chip on a module substrate or another electronic device as external connection terminals for the electrical connection between the semiconductor chip and the module substrate or another electronic device. However, the arrangement of solder balls is restricted by the JEDEC (Joint Electron Device Engineering Council) standards, and the location of the solder ball may be inconsistent with the location of a TSV. Thus, in order to electrically connect the solder ball and the TSV, a printed circuit board (PCB) or a rearrangement interconnection for interconnection routing is disposed between the solder ball and the semiconductor chip. Thus, the location of the TSV may be restricted by the arrangement of solder balls, and the electrical signal path may be increased by the introduction of a separate substrate."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "An embodiment of the present invention relates to a semiconductor device that can overcome the restriction due to the arrangement of external connection terminals, thus allowing more latitude in placing a TSV or a connection pad.

"In one embodiment, a semiconductor device includes: a semiconductor chip including a front surface with circuit elements and interconnections integrated thereon and a rear surface opposite to the front surface; buried conductive lines comprising a first buried conductive line and a second buried conductive line, wherein the first buried conductive line is vertically separated from a second buried conductive line with respect to the front surface of the semiconductor chip; a first conductive via connected to the buried conductive line by piercing from the front surface of the semiconductor chip; and a second conductive via connected to the buried conductive line by piercing from the rear surface of the semiconductor chip.

"In another embodiment, a semiconductor device includes: a semiconductor chip including a front surface and a rear surface opposite to the front surface; buried conductive lines comprising a first buried conductive line and a second buried conductive line, wherein the first buried conductive line is vertically separated from a second buried conductive line with respect to the front surface of the semiconductor chip; a first conductive via connected to the first buried conductive line by piercing from the front surface of the semiconductor chip; a second conductive via connected to the second buried conductive line by piercing from the rear surface of the semiconductor chip; and a third conductive via disposed to connect the first buried conductive line and the second buried conductive line.

"In another embodiment, a semiconductor device includes: a semiconductor chip including a front surface that exposes first connection terminals and a rear surface that is opposite to the front surface and exposes second connection terminals separated from the first connection terminals; and an inner interconnection structure including horizontal buried conductive lines and vertical connection vias disposed to pierce the semiconductor chip to connect the first connection terminals and the second connection terminals.

"The buried conductive lines may include: first buried conductive lines parallel to the front surface of the semiconductor chip and separated from each other to constitute a first array; and second buried conductive lines separated from the first array vertically and arranged across the first array to constitute a second array.

"The connection vias may further include a third conductive via disposed to interconnect the first buried conductive line and the second buried conductive line.

"The semiconductor device may further include dielectric vias disposed to selectively electrically separate one of the first buried conductive lines and the second buried conductive lines to a plurality of conductive line portions by piercing from one of the front surface and the rear surface of the semiconductor chip."

For the URL and additional information on this patent, see: Seo, Hyun Chul; Lee, Seung Yeop. Semiconductor Device Including Inner Interconnection Structure Able to Conduct Signals Or Voltages in the Semiconductor Chip with Vertical Connection Vias and Horizontal Buried Conductive Lines. U.S. Patent Number 8772937, filed June 17, 2011, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772937.PN.&OS=PN/8772937RS=PN/8772937

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Electronics Newsweekly


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