Patent number 8772110 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Embodiments of the present invention relate generally to a semiconductor device with active regions having a fin structure, and more specifically to a semiconductor device and a method of manufacturing the same not to generate a parasitic transistor while reducing a thickness of a wall oxide film formed at sidewalls of an active region.
"As semiconductor devices have become more highly integrated, active regions has been scaled down. As a result, the channel length of transistors formed in the active region has been reduced.
"If the channel length of transistors becomes smaller, the size of a channel region also becomes smaller, and short channel effects such as drain induced barrier lowering (DIBL) occur.
"Thus, various methods for maximizing the performance of devices while reducing the size of elements formed over a substrate have been researched and developed. One of these various methods is a transistor having a fin structure.
"The fin transistor is a transistor with a 3-dimensional channel structure that includes an active region having a protruded channel region, rather than a device isolation film, so that a gate may surround both side surfaces as well as the upper surface of the active region. Through this structure, the channel region is extended so that channels may be formed on three surfaces of the active region (upper surfaces and both side surfaces), thereby improving driving current characteristics.
"In such fin structure, the width of the fin is increased in order to increase cell current. One of methods of increasing the width of the fin is to reduce a thickness of an insulating film (wall oxide film) buried in the lower portion of a device isolation film. That is, a space where the device isolation film is formed is determined by the width of the active region and the thickness of the wall oxide film formed over the active region. If the thickness of the wall oxide film is reduced while the space of the device isolation film is maintained, the width of the active region can be increased corresponding to the reduction, thereby increasing the width of the fin.
"However, although the cell current is increased when the thickness of the wall oxide film is reduced, the wall oxide film protrudes above the device isolation film around the boundary of the device isolation film and the gate, and the protruded wall oxide film serves as a gate insulating film. In such a device, since the thickness of the wall oxide film is low, a parasitic transistor having a lower threshold voltage than that of the fin transistor is generated around the boundary of the device isolation film and the gate. As a result, the overall threshold voltage of the cell becomes lower.
"Accordingly, it is desirable to establish a new method for reducing the thickness of the wall oxide film without generating a parasitic transistor."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "Various embodiments of the present invention are directed to preventing a threshold voltage of a cell transistor from being lowered by a parasitic transistor by implanting a inert gas into a wall oxide film to remove the wall oxide film adjacent to a gate region and form a gate insulating film at the removed location.
"Various embodiments of the present invention are also directed to improving an operating characteristic of the semiconductor device by selectively extending only a width of a gate adjacent to an active region in the gate region.
"According to an embodiment of the present invention, a semiconductor device comprises: an active region defined by a device isolation film and the active region having a fin structure protruded in a gate region; a gate formed in the gate region over the fin structure; a wall oxide film located between the device isolation film and the active region; and a gate insulating film located between the gate and the active region, wherein a portion of the gate insulating film is provided below an upper surface of the device isolation film.
"The wall oxide film has a thickness thinner than that of the gate insulating film.
"An extended portion of the gate is disposed below an upper surface of the device isolation film and extends past a side surface of the fin structure.
"The extended portion of the gate covers the portion of the gate insulating film provided below the upper surface of the device isolation film.
"According to another embodiment of the present invention, a method of manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a trench for device isolation that defines an active region; forming a wall oxide film having a first thickness in the inner surface of the trench for device isolation; forming a device isolation film in the trench for device isolation; etching the active region and the device isolation film to form a recess with a first depth over the active region and a second depth greater than the first depth over the device isolation film; forming a moat by removing portions of the wall oxide film adjacent to the active region exposed by the recess; forming a gate insulating film having a second thickness over the portion of active region exposed by the recess and the moat; and forming a gate in the recess.
"The method further comprises implanting a inert gas into the wall oxide film before forming the device isolation film.
"The inert gas includes at least one selected from Ar and F.
"The implanting-a-inert gas comprises performing a slant implanting process so that the inert gas may be implanted only into the wall oxide film formed at sidewalls of the trench for the device isolation.
"The forming-a-moat comprises performing a cleaning process after forming the recess to remove the wall oxide film protruded rather than the device isolation film around the boundary of the active region and the device isolation film, and the wall oxide film buried in the lower portion of the device isolation film.
"The forming-a-gate-insulating-film comprises forming an insulating film in the active region so as to bury the moat.
"The forming-a-moat comprises partially removing the device isolation film while removing the wall oxide film so as to extend partially a width of the recess.
"The forming-a-moat comprises removing the device isolation film adjacent to the active region exposed by the recess while removing the wall oxide film.
"The forming-a-moat comprises: implanting an inert gas into the wall oxide film and the device isolation film adjacent to the active region expose by the recess; and performing a cleaning process on the recess.
"The forming-a-moat-comprises forming the width of the moat to be larger than the thickness of the gate insulating film.
"The forming-a-gate comprises forming a gate within the recess so as to bury the moat.
"The implanting-a-inert gas comprises implanting the inert gas into the side surface as well as the bottom surface of the recess.
"The inert gas includes at least one selected from Ar and F."
URL and more information on this patent, see: Baek, Seung Joo. Semiconductor Device Having Fin Structure and Method of Manufacturing the Same. U.S. Patent Number 8772110, filed
Keywords for this news article include: Electronics,
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