News Column

Patent Issued for Panel and Method for Fabricating the Same

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Huang, Kuo-Yu (Hsin-Chu, TW); Huang, Te-Chun (Hsin-Chu, TW), filed on May 29, 2012, was published online on July 8, 2014.

The patent's assignee for patent number 8772796 is AU Optronics Corp. (Science-Based Industrial Park, Hsin-Chu, TW).

News editors obtained the following quote from the background information supplied by the inventors: "The document relates to a panel and a method for fabricating the same, and particularly to a fabrication method during which wiring traces can be protected and a panel fabricated by the method.

"In a fabrication process for display, with the development of high resolution and slim border for the small and medium size panel of thin film transistor liquid crystal display (TFT-LCD), the number of the photolithography-and-etching process (PEP) is increased for improvement of the aperture ratio of the pixel and slim border properties of the TFT display panel. However, in a mass production, a bottleneck occurs due to the numerous photolithography-and-etching processes. Moreover, more defects are likely generated, causing a low yield, as more processing procedures are performed.

"Accordingly, there is still a need for a novel panel and the fabricating method of the panel to reduce the mask number used in the fabrication so as to have a convenient process and defect reduction for yield improvement."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "According to an objective of the disclosure, a panel according to an exemplary embodiment is provided. The panel includes a substrate, a first patterned conductive layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, a patterned semiconductor layer, a third patterned conductive layer, a protection layer, and a patterned conductive film. The substrate is defined with a pixel region and a wiring region on at least one side of the pixel region. The first patterned conductive layer is disposed on the substrate. The first patterned conductive layer includes at least one first electrode line, at least one first electrode, and at least one wiring trace. The first electrode and the first electrode line are connected to each other and both disposed in the pixel region. The wiring trace is disposed in the wiring region. The first insulation layer is disposed to cover the pixel region, the wiring region, and the first patterned conductive layer. The second patterned conductive layer is disposed on the first insulation layer. The second patterned conductive layer includes at least one second electrode which is disposed on the first insulation layer in the pixel region. The second insulation layer is disposed to cover the second electrode in the pixel region, the wiring region, and the first insulation layer above the wiring trace. The patterned semiconductor layer is disposed on the second insulation layer. The patterned semiconductor layer includes at least one first portion corresponding to the first electrode and at least one second portion corresponding to the wiring trace. The third patterned conductive layer is disposed on the second insulation layer. The third patterned conductive layer includes at least one second electrode line, at least one third electrode connected to the second electrode line, and at least one fourth electrode. The third electrode, the second electrode line, and the fourth electrode are disposed in the pixel region. The first electrode, the first portion of the patterned semiconductor layer, and the third electrode are disposed to form a transistor. The fourth electrode and the second electrode are correspondingly disposed to form a storage capacitor. The protection layer is disposed to cover the third patterned conductive layer and the second insulation layer in the pixel region. The patterned conductive film is disposed on the protection layer in the pixel region. The patterned conductive film includes at least one pixel electrode which is connected to the transistor and the storage capacitor.

"According to an objective of the disclosure, a method of fabricating a panel according to an exemplary embodiment is provided. The method of fabricating a panel includes steps as follows. First, a substrate is provided. The substrate is defined with a pixel region and a wiring region on at least one side of the pixel region. Next, a first patterned conductive layer is formed on the substrate. The first patterned conductive layer includes at least one first electrode line, a first electrode connected to the at least one first electrode line, and at least one wiring trace. The first electrode and the first electrode line are disposed in the pixel region. The wiring trace is disposed in the wiring region. A first insulation layer is formed to cover the pixel region, the wiring region, and the first patterned conductive layer. A second patterned conductive layer is formed on the first insulation layer. The second patterned conductive layer includes at least one second electrode disposed on the first insulation layer in the pixel region. A second insulation layer is formed and covers the second electrode in the pixel region, the wiring region, and the first insulation layer above the wiring trace. A patterned semiconductor layer is formed on the second insulation layer. The patterned semiconductor layer includes at least one first portion corresponding to the first electrode and at least one second portion corresponding to the wiring trace. A third patterned conductive layer is formed on the second insulation layer. The third patterned conductive layer includes at least one second electrode line, at least one third electrode connected to the second electrode line, and at least one fourth electrode. The third electrode, the second electrode line, and the fourth electrode are disposed in the pixel region. The first electrode, the first portion of the patterned semiconductor layer, and the third electrode are disposed to form a transistor. The fourth electrode and the second electrode are correspondingly disposed to form a storage capacitor. A protection layer is formed and covers the third patterned conductive layer and the second insulation layer in the pixel region. A patterned conductive film is formed on the protection layer in the pixel region. The patterned conductive film includes at least one pixel electrode connected to the transistor and the storage capacitor.

"These and other objectives of the disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the exemplary embodiment that is illustrated in the various figures and drawings."

For additional information on this patent, see: Huang, Kuo-Yu; Huang, Te-Chun. Panel and Method for Fabricating the Same. U.S. Patent Number 8772796, filed May 29, 2012, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772796.PN.&OS=PN/8772796RS=PN/8772796

Keywords for this news article include: Electronics, Semiconductor, Photolithography, AU Optronics Corp..

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Source: Electronics Newsweekly


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