News Column

Patent Issued for Multi-Purpose Architecture for CCD Image Sensors

July 23, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Ciccarelli, Antonio S. (Webster, NY); Meisenzahl, Eric J. (Ontario, NY), filed on May 25, 2011, was published online on July 8, 2014.

The assignee for this patent, patent number 8773563, is Truesense Imaging, Inc. (Rochester, NY).

Reporters obtained the following quote from the background information supplied by the inventors: "Charge-Coupled Device (CCD) image sensors capture images using an array of photosensitive areas that collect charge in response to light. FIG. 1 is a simplified block diagram of a prior art CCD image sensor. Image sensor 100 includes vertical charge-coupled device (VCCD) shift registers 102 that each include a column of charge storage elements 104. For simplicity, only three VCCD shift registers are shown in FIG. 1. When an image is captured by image sensor 100, charge packets 106 in the VCCDs 102 are shifted in parallel one row at a time to charge storage elements 108 in horizontal CCD (HCCD) shift register 110. Each row of charge in HCCD 110 is shifted serially one charge storage element 108 at a time to output circuit 112. Output circuit 112 converts the charge packets into analog voltage output signal (V.sub.out). Other components in an imaging system typically process and redisplay the pixels to reproduce the captured image.

"Depending on frame rate requirements, it may be necessary to increase the speed of charge transfer from the image sensor to the rest of the imaging system. Common approaches include increasing the transfer rate of the shift registers or providing additional output structures where each output handles only a portion of the total number of pixels. A commonly found example of a prior art image sensor with multiple output structures is shown in FIG. 2. The gate electrodes (not shown) overlying the array of pixels 200 run continuously across the entire array. The clocking signals applied to the gate electrodes shift charge out of the array and into one of four different output structures 202, 204, 206, 208. This arrangement is sometimes referred to as quadrant readout architecture.

"Additionally, an image sensor having the architecture shown in FIG. 2 can be constructed and driven with a flexible clocking scheme such that the pixels are readout of pixel array 200 in arrangements other than the four output quadrant mode. For example, in image sensors such as the commercially available Kodak KAI-01050 CCD image sensor, pixels can be alternatively readout into any one, two or even three output structures. This flexible readout architecture enables a camera designer to trade off frame rate by deciding how many outputs a camera will support. Using fewer outputs generally reduces camera electronics costs, simplifies image reconstruction and improves image quality.

"In some situations, it is desirable to improve the sensitivity and signal-to-noise ratio of an image sensor through charge amplification or multiplication. FIG. 3 illustrates a prior art image sensor that includes an extended HCCD shift register for the purpose of amplifying the signal of a captured image. HCCD shift register 300 and charge multiplication HCCD shift register 302 both include charge storage elements that are each driven by one or more gate electrodes (not shown). Charge is shifted from HCCD shift register 300 into charge multiplication shift register 302. Charge multiplication or amplification occurs during charge transfer in charge multiplication shift register 302 through the application of large voltages to the overlying gate electrodes in the shift register 302. The resulting large electric fields within the silicon produce a signal larger than originally detected in the pixels in pixel array 304. Many factors control the amount of signal amplification including the amount of charge present, the extent of the electric field strength and the number of amplifying stages in the charge multiplication shift register 302. U.S. Pat. Nos. 4,912,536, 5,337,340, 6,444,968, 6,784,412, 7,139,023 and 7,420,605 disclose various methods and structures for charge multiplication.

"One limitation to charge multiplying HCCD shift register 302 in some image sensors is be the increased die size and associated higher manufacturing costs. In addition, if the number of phases in the charge multiplying HCCD shift register 302 is not an even multiple of HCCD shift register 300, then line and frame rates are degraded as result of having to spend additional time clocking the extra HCCD phases not associated to image data.

"U.S. Pat. No. 7,522,205 describes an architecture where the HCCD shift register is operated in normal fashion for full image resolution readout and alternately as a charge multiplication HCCD shift register for half image resolution readout. FIG. 4 depicts the operation of a CCD image sensor during full image resolution readout mode as disclosed in U.S. Pat. No. 7,522,205. FIG. 5 illustrates the operation of the CCD image sensor shown in FIG. 4 during the charge multiplication mode. HCCD shift register 400 can be operated to shift charge to one or two outputs in normal readout (FIG. 4) by means of independent sets of HCCD clocks, H.sub.A and H.sub.B. During charge multiplication readout mode (FIG. 5), both H.sub.A and H.sub.B are operated such that charge transfer occurs in only one direction and H.sub.A clock voltages are increased to achieve the desired charge multiplication. A split fast dump row structure 500, 502 is used to independently control whether or not charge packets from the left side 504 or the right side 506 of the pixel array are allowed to transfer into HCCD shift register 400. FIG. 5 illustrates how charge packets in the columns associated with the left side 504 are prevented from dropping down into HCCD shift register 400 by the split fast dump row structure 500 so as to avoid interfering with the charge packets being readout from the previous line on the right side 506 of the pixel array. The charge multiplication mode shown in FIG. 5 can keep the frame rate constant but produces a half resolution image because half of the image is lost or thrown away through the fast dump row structure 500."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "According to a first aspect, a Charge-Coupled Device (CCD) image sensor is configured to operate in multiple modes of operation, including a full resolution charge multiplication mode. By way of example only, other modes of operation can include a full resolution image readout mode or a reduced resolution image readout mode.

"The CCD image sensor can include a pixel array having multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers. The independently-controllable gate electrodes are arranged into physically separate and distinct sections that are non-continuous or disrupted across the plurality of VCCD shift registers in the pixel array. The CCD image sensor can include horizontal charge-coupled device (HCCD) shift registers each including charge storage elements. Each charge storage element can be connected to a respective VCCD shift register to receive charge directly from the respective VCCD shift register. The CCD image sensor can include one or more timing generators for producing VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and into respective HCCD shift registers. The same or different timing generators can produce HCCD clocking signals applied to respective gate electrodes for shifting charge through the HCCD shift registers. The timing generator or generators can be operable to produce VCCD and HCCD clocking signals for the full resolution charge multiplication mode as well as for other operating modes, such as a full resolution image readout mode.

"The image sensor can be included in an image capture device. The timing generator or generators that are configured to produce VCCD clocking signals or HCCD clocking signals can be included in the image capture device. The image capture device can include a processor operable to control the production of VCCD or HCCD clocking signals based on the respective operating mode of the image capture device.

"According to another aspect, a method for producing an image sensor configured to operate in multiple modes of operation, including a full resolution charge multiplication mode includes forming a first section of gate electrodes over a portion of VCCD shift registers and forming a second section of gate electrodes over a remaining portion of the VCCD shift registers. A physical gap is formed between the two sections of gate electrodes such that the first and second sections of gate electrodes are physically separated and electrically isolated from each other.

"According to yet another aspect, a method for operating an image sensor configured to operate in multiple modes of operation, including a full resolution charge multiplication mode includes applying VCCD clocking signals to one section of gate electrodes to shift charge from the VCCD shift registers corresponding to one section of gate electrodes directly into respective charge storage elements in a first HCCD shift register. VCCD clocking signals can be applied to another section of gate electrodes to shift charge from the VCCD shift registers corresponding to the other section of gate electrodes directly into respective charge storage elements in a second HCCD shift register. The method can further include applying HCCD clocking signals to gate electrodes disposed over the first HCCD shift register to shift the charge through the HCCD shift register and into a third HCCD shift register. HCCD clocking signals can be applied to gate electrodes disposed over the third HCCD shift register to shift the charge through the third HCCD shift register and multiply the charge as the charge shifts through the third HCCD shift register. HCCD clocking signals can be applied to gate electrodes disposed over the second HCCD shift register to shift the charge through the HCCD shift register into a fourth HCCD shift register. HCCD clocking signals can be applied to gate electrodes disposed over the fourth HCCD shift register to shift the charge through the fourth HCCD shift register and multiply the charge as the charge shifts through the fourth HCCD shift register."

For more information, see this patent: Ciccarelli, Antonio S.; Meisenzahl, Eric J.. Multi-Purpose Architecture for CCD Image Sensors. U.S. Patent Number 8773563, filed May 25, 2011, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8773563.PN.&OS=PN/8773563RS=PN/8773563

Keywords for this news article include: Truesense Imaging Inc.

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Source: Journal of Engineering


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