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Patent Issued for Method of Manufacturing Semiconductor Device Using Stress Memorization Technique

July 25, 2014



By a News Reporter-Staff News Editor at Health & Medicine Week -- A patent by the inventors Kim, Seok-Hoon (Hwaseong-si, KR); Kim, Sang-Su (Yongin-si, KR); Koh, Chung-Geun (Seoul, KR); Lee, Sun-Ghil (Goyang-si, KR); Joe, Jin-Yeong (Suwon-si, KR), filed on June 13, 2012, was published online on July 8, 2014, according to news reporting originating from Alexandria, Virginia, by NewsRx correspondents (see also Samsung Electronics Co., Ltd.).

Patent number 8772095 is assigned to Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present inventive concept relates to a method of manufacturing a semiconductor device using a stress memorization technique (SMT).

"The conductivity of a channel region of a metal oxide semiconductor (MOS) transistor may be increased to improve the performance of the MOS transistor. For example, the lattice structure of the channel region may altered to increase the charge-carrier mobility and hence, the conductivity of the channel region.

"A stress memorization technique (STM) is one of the techniques that can be used to alter the lattice structure of the channel region. Specifically, an STM entails forming an amorphous region near a channel region in which the channel of the MOS transistor will form, and annealing the amorphous region while a stress inducing layer is located on the amorphous region. The amorphous region is thus recrystallized in a state in which stress is exerted thereon by the stress inducing layer. As a result, deformed crystals are formed. The deformed crystals maintain their deformed state even after the stress inducing layer is removed. Accordingly, the stress is considered to be memorized in the deformed crystals.

"The deformed crystals act as a stressor on the channel region, affecting the lattice structure of the channel region, and thereby increasing the charge-carrier mobility.

"Meanwhile, during the recrystallization process of SMT, the crystals tend to grow at different rates in various crystallographic directions because the amorphous region is recrystallized under the stress induced therein by the stress inducing layer. For example, in the recrystallization process, the crystal growth rate may be greater in a crystallographic direction than in a crystallographic direction. In this case, a point at which crystal growth pinches off can appear near a (111) facet, thus creating a stacking fault, i.e., a defective region. Halo boron segregation can occur at the defective region, causing problems such as a reduction in the desired threshold voltage and undesired amounts of off-leakage current."

In addition to the background information obtained for this patent, NewsRx journalists also obtained the inventors' summary information for this patent: "According to one aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device which includes providing a structure that has a substrate and a gate electrode at an upper part of the substrate, forming doped amorphous source/drain regions to both sides of the gate electrode, respectively, such that the amorphous source/drain regions are spaced from each other across a channel region of the substrate, and subsequently annealing the substrate to recrystalize the doped amorphous source/drain regions, and in which the doped amorphous source/drain regions are formed at least by implanting, into the substrate, impurities that will minimize differences between crystal growth rates in different crystallographic directions during the annealing of the substrate.

"According to another aspect of the present inventive concept, there is provided a method of manufacturing a semiconductor device which includes providing a substrate and a gate electrode disposed on an upper part of the substrate such that the substrate has source/drain regions located to the sides of the gate electrode, respectively, and a channel region interposed between the source/drain regions, and inducing stress in the channel region of the substrate by growing crystals in the source/drain regions at substantially the same rates in both and crystallographic directions substantially perpendicular and parallel to an upper surface of substrate, respectively, and in which the inducing of stress in the channel region includes amorphizing the source/drain regions to form amorphous source/drain regions, and subsequently subjecting the amorphous source/drain regions to a solid phase epitaxial (SPE) growth process that recrystallizes the amorphous source/drain regions.

"According to still another aspect of the present inventive concept, there is provided a method of manufacturing a semiconductor device which includes providing a substrate and a gate electrode at an upper part of the substrate such that the substrate has source/drain regions located to the sides of the gate electrode, performing a pre-amorphization implantation (PAI) process that amorphizes the source/drain regions, implanting C or N into the amorphized source/drain regions, forming a stress inducing layer that covers the substrate, subsequently recrystallizing the amorphized source/drain regions by annealing the substrate, and removing the stress inducing layer after the substrate has been annealed.

"According to yet another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device which includes providing a substrate and a gate electrode disposed on an upper part of the substrate such that the substrate has source/drain regions located to the sides of the gate electrode, amorphizing the source/drain regions by implanting C or N into the source/drain regions in a temperature range of -20 to -100.degree. C., forming a stress inducing layer over the substrate, and recrystallizing the amorphized source/drain regions by annealing the substrate while the stress inducing layer is disposed over the substrate."

URL and more information on this patent, see: Kim, Seok-Hoon; Kim, Sang-Su; Koh, Chung-Geun; Lee, Sun-Ghil; Joe, Jin-Yeong. Method of Manufacturing Semiconductor Device Using Stress Memorization Technique. U.S. Patent Number 8772095, filed June 13, 2012, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772095.PN.&OS=PN/8772095RS=PN/8772095

Keywords for this news article include: Semiconductor, Crystal Growth, Samsung Electronics Co. Ltd..

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Health & Medicine Week


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