News Column

Patent Issued for Method for Package-On-Package Assembly with Wire Bonds to Encapsulation Surface

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Co, Reynaldo (Santa Cruz, CA); Mirkarimi, Laura (Sunol, CA), filed on January 29, 2013, was published online on July 8, 2014.

The assignee for this patent, patent number 8772152, is Invensas Corporation (San Jose, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "Embodiments of the invention herein relate to various structures and ways of making microelectronic packages which can be used in package-on-package assemblies, and more particularly, to such structures which incorporate wire bonds for as part of the package-on-package connections.

"Microelectronic devices such as semiconductor chips typically require many input and output connections to other electronic components. The input and output contacts of a semiconductor chip or other comparable device are generally disposed in grid-like patterns that substantially cover a surface of the device (commonly referred to as an 'area array') or in elongated rows which may extend parallel to and adjacent each edge of the device's front surface, or in the center of the front surface. Typically, devices such as chips must be physically mounted on a substrate such as a printed circuit board, and the contacts of the device must be electrically connected to electrically conductive features of the circuit board.

"Semiconductor chips are commonly provided in packages that facilitate handling of the chip during manufacture and during mounting of the chip on an external substrate such as a circuit board or other circuit panel. For example, many semiconductor chips are provided in packages suitable for surface mounting. Numerous packages of this general type have been proposed for various applications. Most commonly, such packages include a dielectric element, commonly referred to as a 'chip carrier' with terminals formed as plated or etched metallic structures on the dielectric. These terminals typically are connected to the contacts of the chip itself by features such as thin traces extending along the chip carrier itself and by fine leads or wires extending between the contacts of the chip and the terminals or traces. In a surface mounting operation, the package is placed onto a circuit board so that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads. The package can be permanently bonded in place by heating the assembly so as to melt or 'reflow' the solder or otherwise activate the bonding material.

"Many packages include solder masses in the form of solder balls, typically about 0.1 mm and about 0.8 mm (5 and 30 mils) in diameter, attached to the terminals of the package. A package having an array of solder balls projecting from its bottom surface is commonly referred to as a ball grid array or 'BGA' package. Other packages, referred to as land grid array or 'LGA' packages are secured to the substrate by thin layers or lands formed from solder. Packages of this type can be quite compact. Certain packages, commonly referred to as 'chip scale packages,' occupy an area of the circuit board equal to, or only slightly larger than, the area of the device incorporated in the package. This is advantageous in that it reduces the overall size of the assembly and permits the use of short interconnections between various devices on the substrate, which in turn limits signal propagation time between devices and thus facilitates operation of the assembly at high speeds.

"Packaged semiconductor chips are often provided in 'stacked' arrangements, wherein one package is provided, for example, on a circuit board, and another package is mounted on top of the first package. These arrangements can allow a number of different chips to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation by providing a short interconnection between packages. Often, this interconnect distance is only slightly larger than the thickness of the chip itself. For interconnection to be achieved within a stack of chip packages, it is necessary to provide structures for mechanical and electrical connection on both sides of each package (except for the topmost package). This has been done, for example, by providing contact pads or lands on both sides of the substrate to which the chip is mounted, the pads being connected through the substrate by conductive vias or the like. Solder balls or the like have been used to bridge the gap between the contacts on the top of a lower substrate to the contacts on the bottom of the next higher substrate. The solder balls must be higher than the height of the chip in order to connect the contacts. Examples of stacked chip arrangements and interconnect structures are provided in U.S. Patent App. Pub. No. 2010/0232129 ('the '129 Publication'), the disclosure of which is incorporated by reference herein in its entirety.

"Microcontact elements in the form of elongated posts or pins may be used to connect microelectronic packages to circuit boards and for other connections in microelectronic packaging. In some instances, microcontacts have been formed by etching a metallic structure including one or more metallic layers to form the microcontacts. The etching process limits the size of the microcontacts. Conventional etching processes typically cannot form microcontacts with a large ratio of height to maximum width, referred to herein as 'aspect ratio'. It has been difficult or impossible to form arrays of microcontacts with appreciable height and very small pitch or spacing between adjacent microcontacts. Moreover, the configurations of the microcontacts formed by conventional etching processes are limited.

"Despite all of the above-described advances in the art, still further improvements in making and testing microelectronic packages would be desirable."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "A microelectronic assembly may include a substrate having a first and second opposed surfaces. A microelectronic element can overlie the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements may be electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases. Each wire bond can define an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds may be defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

"Various package structures are disclosed herein which incorporate wire bonds functioning as vertical connections extending upwardly from conductive elements, e.g., conductive pads on a substrate. Such wire bonds can be used in making package on package electrical connections with a microelectronic package overlying a surface of a dielectric encapsulation. In addition, various embodiments of methods are disclosed herein for making a microelectronic package or a microelectronic assembly.

"Thus, a method of making a microelectronic package according to an aspect of the invention can include a) feeding a metal wire segment having a predetermined length out of a capillary of a bonding tool; b) using the bonding tool to bond a portion of the metal wire to a conductive element exposed at a first surface of a substrate, thereby forming a base of a wire bond on the conductive element; c) clamping a portion of the wire within the bonding tool; d) cutting the metal wire at a location between the clamped portion and the base portion to at least partially define an end surface of the wire bond, an edge surface of the wire bond being defined between the base and the end surface; e) repeating steps (a) through (d) to form a plurality of wire bonds to a plurality of the conductive elements of the substrate; and e) then forming a dielectric encapsulation layer overlying the surface of the substrate, wherein the encapsulation layer is formed so as to at least partially cover the surface of the substrate and portions of the wire bonds, such that unencapsulated portions of the wire bonds are defined by a portion of at least one of an end surface or of an edge surface thereof that is uncovered by the encapsulation layer.

"Thus, in accordance with an aspect of the invention, a metal wire segment having a predetermined length can be fed out of a capillary of a bonding tool. The bonding tool can be used to bond a portion of the metal wire to a conductive element exposed at a first surface of a substrate. Such bonding can form a base of the wire bond on the conductive element. A portion of the wire can be clamped after forming the bond with the conductive element. The portion of the wire clamped can be within the bonding tool. The metal wire can be cut at a location between the clamped portion and the base portion, and cutting the wire may at least partially define an end surface of the wire bond. An edge surface of the wire bond can be defined between the base and the end surface. The foregoing can be repeated to form a plurality of wire bonds to a plurality of the conductive elements of the substrate. Then, a dielectric encapsulation layer can be formed overlying the surface of the substrate. The encapsulation layer can be formed so as to at least partially cover the surface of the substrate and portions of the wire bonds. Unencapsulated portions of the wire bonds can be defined by a portion of at least one of an end surface or of an edge surface thereof that is uncovered by the encapsulation layer.

"In one example, the metal wire can be cut only partially therethrough. The bonding tool can be moved away from the surface of the substrate while the portion of the wire remains clamped. In such process, the wire can be caused to break at the location of the cut. An end surface can be formed by the cut and the break.

"In one example, the cut can be made completely through the wire segment in a direction substantially perpendicular to the edge surface of the wire bond. An end surface of the wire bond can be formed by the cut.

"In one example, at least one microelectronic element can overlie the first surface of the substrate. The substrate can have a first region and a second region and the microelectronic element can be located within the first region, e.g., as overlying the first region. The conductive elements can be located within the second region, e.g., as conductive elements exposed at the first surface therein. The conductive elements can be electrically connected to the at least one microelectronic element. The dielectric encapsulation layer can be formed overlying the first surface of the substrate in at least the second region thereof, but may overlie at least a portion of the first surface in the first region as well as the second region.

"In one example, the package can be configured such that a first wire bond of the wire bonds is adapted for carrying a first signal electric potential and a second wire bond of the wire bonds is adapted for simultaneously carrying a second signal electric potential different from the first signal electric potential.

"In one example, the metal wire segment can be cut using a laser mounted on the bonding tool. In such example, the capillary of the bonding tool can define a face thereof through which the wire segment is fed. The laser can be mounted on or with the bonding tool such that a cutting beam can be directed to a location of the wire segment positioned between the face of the bonding tool and the base of the wire bond.

"In one example, the bonding tool can include a capillary defining a face thereof through which the wire segment is fed. The capillary may include an opening in a side wall thereof, and the laser can be mounted on or with the bonding such that a cutting beam can pass through the opening to a location of the wire segment positioned within the capillary.

"In one example, the laser can be one of: C02, Nd:YAG, or a Cu vapor laser.

"In one example, the metal wire can be cut using a cutting edge that extends within the capillary. In one example, the cutting edge can extend in a direction toward a wall of the capillary opposite the wire segment. In one example, the metal wire can be cut using the cutting edge as a first cutting edge, and in combination with a second cutting edge that extends within the capillary. The second cutting edge may be positioned in opposition with the first cutting edge.

"In one example, the capillary may define a face through which the wire segment can be fed. The metal wire can be cut using a cutting instrument having first and second opposing cutting edges. The cutting instrument can be mounted on or with the bonding tool in such way that the wire can be cut at a location positioned between the face of the bonding tool and the base of the wire bond.

"One example of the method may include positioning a stencil over the substrate. The stencil can have a plurality of openings therein that overlie and expose at least portions of the conductive elements. The openings can define respective edges positioned at a first height over the substrate. The wire segment can be cut by lateral movement of the wire against the edge of the stencil opening.

"A method of making a microelectronic package according to an aspect of the invention can include: positioning a stencil over an in-process unit including a substrate having a first surface and a second surface remote therefrom. A microelectronic element can be mounted to the first surface of the substrate. A plurality of conductive elements can be exposed at the first surface. In an example, at least some of the conductive elements can be electrically connected to the microelectronic element. The stencil can have a plurality of openings therein that overlie and expose at least portion of the conductive elements. The openings may define respective edges which are positioned at a first height over the substrate.

"In accordance with such aspect, the method can include forming a wire bond by a process including feeding a metal wire out of a capillary of a bonding tool such that a predetermined length extends beyond the face of the capillary and defines a metal wire segment. A portion of the wire segment can be joined to a conductive element of the plurality of conductive elements to form a base of the wire bond. At least a portion of the metal wire segment can be sheared from another portion of the wire connected thereto by lateral movement of the wire against the edge of the stencil opening to separate the wire bond from a remaining portion of the wire. The shearing of the metal wire can define an end surface of the wire bond, the wire bond having an edge surface extending between the base and the end surface. The feeding out of the metal wire, bonding, and shearing thereof as described above can be repeated a plurality of times using one or more openings of the stencil to form a plurality of wire bonds on a plurality of the conductive elements.

"In an example of such method, a dielectric encapsulation layer can be formed on the in-process unit, wherein the encapsulation layer is formed so as to at least partially cover the first surface and portions of the wire bonds. Unencapsulated portions of the wire bonds can be defined by a portion of at least one of the end surface or of the edge surface thereof which is uncovered by the encapsulation layer.

"In an example of such method, a portion of the metal wire which extends beyond a face of the capillary and which remains after the shearing of the metal wire can be of a length sufficient to form at least a base of a subsequent wire bond.

"In an example of the method, the stencil can define a thickness in a direction of an axis extending of one of the holes, e.g., in a vertical direction away from a surface of the substrate. Some or all of the holes can have a consistent or constant diameter through the thickness of the stencil.

"In an example of the method, the stencil can define a thickness in a direction of an axis of one of the holes or openings, e.g., in a vertical direction away from a surface of the substrate. Some or all of the holes or openings in the stencil can be tapered from a first width or smaller diameter at an exposed edge within the opening to a second larger width or greater diameter at another location within the hole or opening and closer to the substrate.

"In one example, the stencil may include an edge member having a first thickness in a direction of thickness of the substrate extending along one or more edges of the substrate. The first thickness can define a first height. A central portion may include the holes or openings and can be bounded by the edge member. The central portion can have an outer surface facing away from the substrate. The outer surface can be disposed at the first height. The central portion can have a thickness which is less than the first thickness."

For more information, see this patent: Co, Reynaldo; Mirkarimi, Laura. Method for Package-On-Package Assembly with Wire Bonds to Encapsulation Surface. U.S. Patent Number 8772152, filed January 29, 2013, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772152.PN.&OS=PN/8772152RS=PN/8772152

Keywords for this news article include: Circuit Board, Semiconductor, Microelectronics, Invensas Corporation.

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Source: Electronics Newsweekly


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