News Column

Patent Issued for Metal Gate Transistors and Fabrication Method

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Semiconductor Manufacturing International (Shanghai) Corporation (Shanghai, CN) has been issued patent number 8772148, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Wang, Xinpeng (Shanghai, CN); He, Qiyang (Shanghai, CN).

This patent was filed on September 18, 2013 and was published online on July 8, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "With the development of semiconductor technology, poly silicon transistors may be unable to match the requirements of the small size semiconductor processes because of their large leakage current and high power consumption. Therefore, metal gate transistors have been developed.

"FIG. 1 illustrates an existing metal gate transistor. The metal gate transistor includes a semiconductor substrate 1. A gate dielectric material layer, a work function material layer and a dummy gate material layer may be sequentially formed on the semiconductor substrate 1. After an etching process, a gate dielectric layer 2, a work function layer 3, and a dummy gate 4 may be formed. The gate dielectric layer 2, the work function layer 3, and the dummy gate 4 may form a stack structure 5. Further, sidewalls of the gate dielectric layer 2, the work function layer 3, and the dummy gate 4 may be on a same plane. A source region (not shown) and a drain region (not shown) may be formed in the semiconductor substrate 1 at both sides of the stack structure 5 by an ion implantation process, followed by an thermal annealing process.

"However, it may have a plurality of high temperature processes for fabricating the existing metal gate transistor. For example, the temperature of an ion implantation process and a rapid thermal annealing process, etc., may all be greater than 300.degree. C. The high temperature processes may cause the gate dielectric layer 2 and the work function layer 3 to shrink, thus widths of the dielectric gate layer 2 and the work function layer 3 may be smaller than a width of the dummy gate 4 along a first direction, i.e., a direction parallel to the direction from the source region to the drain region. Therefore, when the dummy gate 4 is removed to subsequently form a metal gate, a width of the metal gate may be greater than the width of the gate dielectric layer 2 and the width of the work function layer 3, and a length of the metal gate may be greater than a length of the gate dielectric layer 2 and a length of the work function layer 3, the performance of the transistor may be affected.

"In order to solve the above mentioned shrinking problem, a metal gate structure has been developed. As shown in FIG. 2, by controlling the parameters of the etching process of the dummy gate material layer, the gate dielectric material layer and the work function layer, a sidewall 21 of the gate dielectric layer 2 may protrude from a sidewall 31 of the work function layer 3 and a sidewall 41 of the dummy gate 4 after the etching process of the stack 5. Further, the sidewall 21 of the gate dielectric layer 2 may be sloping, i.e., the sidewall 21 of the gate dielectric layer 2 may be not perpendicular to the surface S of the substrate 1.

"FIG. 3 illustrates another metal gate structure to solve the above mentioned shrinking problem. As shown in FIG. 3, by controlling the parameters of the etching process of the dummy gate material layer, the gate dielectric material layer and the work function layer, a sidewall 21 of the gate dielectric layer 2 and a sidewall 31 of the work function layer 3 may both protrude from a sidewall 41 of the dummy gate 4 after the etching process of the stack structure 5. Further, the sidewall 21 of the gate dielectric layer 2 and the sidewall 31 of the work function layer 3 may be sloping, i.e., the sidewall 21 of the gate dielectric layer 2 and the sidewall 31 of the work function layer 3 may be not perpendicular to the surface S of the substrate 1.

"Because the protruding parts of the sidewall 21 of the dielectric layer 2 and the sidewall 31 of the work function layer 3 may compensate shrinkages caused by subsequent processes, the widths of the dielectric layer 3 and the work function layer 3 may be no longer smaller than the width of the metal gate after the gate dielectric layer 2 and the work function layer 3 after shrink, and the lengths of the dielectric layer 3 and the work function layer 3 may not be smaller than the length of the metal gate. Thus, the performance of the transistor may be enhanced.

"However, the above mentioned devices and methods may have certain disadvantages, and may expose the etching processes to challenges. For example, it may be significantly difficult and complex to control the etching processes to cause the gate dielectric layer 2 and the work function layer 3 to protrude outwardly. Further, it may also be difficult to control amount of the protruding. The disclosed methods and devices are directed to solve one or more problems set forth above and other problems."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "One aspect of the present disclosure includes a method for fabricating a metal gate transistor. The method includes providing a semiconductor substrate; and forming a dielectric layer on the semiconductor substrate. The method also includes forming at least one dummy gate on the dielectric layer; and forming a first sidewall spacer around the dummy gate. Further, the method includes forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate and vertical to the semiconductor substrate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask; and removing the dummy gate to form a trench. Further, the method also includes forming a metal gate in the trench; and forming a source region and a drain region in the semiconductor substrate.

"Another aspect of the present disclosure includes a metal gate transistor. The metal gate transistor includes a semiconductor substrate and a gate dielectric layer on the semiconductor substrate. The metal gate transistor also includes a metal gate on the gate dielectric layer, and the gate dielectric layer protruding from the metal gate. Further, the metal gate transistor includes a first sidewall spacer around the metal gate and an interlayer dielectric layer on the semiconductor substrate. Further, the metal gate transistor also includes a source region and a drain region in the semiconductor substrate

"Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure."

For the URL and additional information on this patent, see: Wang, Xinpeng; He, Qiyang. Metal Gate Transistors and Fabrication Method. U.S. Patent Number 8772148, filed September 18, 2013, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772148.PN.&OS=PN/8772148RS=PN/8772148

Keywords for this news article include: Electronics, Semiconductor Manufacturing International.

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Source: Electronics Newsweekly


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