News Column

Patent Issued for Memory Device and Method for Writing Therefor

July 23, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Chen, Yen-Huei (Hsinchu, TW); Wang, Li-Wen (Hsinchu, TW); Lin, Chih-Yu (Hsinchu, TW), filed on July 30, 2012, was published online on July 8, 2014.

The assignee for this patent, patent number 8773923, is Taiwan Semiconductor Manufacturing Company, Ltd. (TW).

Reporters obtained the following quote from the background information supplied by the inventors: "The static random access memory (SRAM) cell generally includes a first inverter, a second inverter, a first pass transistor and a second pass transistor. The first and the second inverters are cross-coupled to form a bistable latch circuit. The first pass transistor is coupled between the first inverter and a first bit line. The second pass transistor is coupled between the second inverter and a second bit line. In order to set or reset the bistable latch circuit, the first and the second pass transistors are enabled by driving a word line and accessed by driving the first and the second bit lines. Each of the first and the second inverters includes a respective p-type metal oxide semiconductor (PMOS) pull-up or load transistor, a respective n-type MOS (NMOS) pull-down or driver transistor, and a respective storage node between the respective PMOS pull-up transistor and the respective NMOS pull-down transistor.

"When the SRAM cell has a static noise margin (SNM) near zero, it may have a weak write property, and thus may inadvertently flip its state. The SNM is a measure of the logic circuit's tolerance to noise in either of the states, i.e. by how much does the input voltage change without disturbing the present logic state. In other words, the SNM represents a measure of cell robustness.

"When the size of the SRAM cell is scaled down, the SRAM cell has the huge device mismatch due to the process variation. A write operation to the SRAM cell is enabled by asserting a desired bit value on the first bit line and a complement of that value on the second bit line, and asserting the word line. A reduced static noise margin (SNM) can lead to cell upsets during a read operation or to unaccessed memory cells during the write operation. When the SRAM cell is powered by an extremely low supply voltage, it suffers a serious write failure due to the huge device mismatch."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In accordance with one aspect of the present disclosure, a memory device is provided. The memory device includes a memory cell, a first pull-down unit and a second pull-down unit coupled to the first pull-down unit. The memory cell is to be written in a specific write cycle. The first and the second pull-down units are sequentially switched in the specific write cycle.

"In accordance with another aspect of the present disclosure, a method for writing a memory cell in a specific write cycle is provided. The method includes the following steps. A first signal having a first transition edge is provided in the specific write cycle. A second signal having a second transition edge is provided in the specific write cycle, wherein the second transition edge and the first transition edge are out of phase. A first voltage level is provided to the memory cell. The first voltage level is lowered to a second voltage level in the specific write cycle for writing the memory cell in response to the first and the second transition edges.

"In accordance with one more aspect of the present disclosure, a method for writing a memory cell in a specific write cycle is provided. The method includes the following steps. A first signal having a first transition edge is provided in the specific write cycle. A second signal having a second transition edge is provided in the specific write cycle, wherein the second transition edge lags behind the first transition edge. A first voltage level is provided to the memory cell. The first voltage level is lowered to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge."

For more information, see this patent: Chen, Yen-Huei; Wang, Li-Wen; Lin, Chih-Yu. Memory Device and Method for Writing Therefor. U.S. Patent Number 8773923, filed July 30, 2012, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8773923.PN.&OS=PN/8773923RS=PN/8773923

Keywords for this news article include: Electronics, Taiwan Semiconductor Manufacturing Company Ltd.

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Source: Journal of Engineering


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