The patent's assignee for patent number 8772928 is
News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to the field of semiconductor integrated circuit devices. More particularly, the present invention relates to an improved integrated circuit chip and its interconnection scheme that are capable of reducing IR drop over the chip.
"In the processes for designing a large-scale integrated semiconductor circuit device, respective blocks of the device are generally designed in parallel to complement device characteristics with one another. During designing the large-scale device, the building-block type of method can be utilized, in which the circuit of the device is divided into a plurality of circuit blocks and each of the circuit blocks is thus designed at the same time. The overall design of the device is then carried out by integrating these constituent blocks.
"An integrated circuit (IC) usually has a large number of circuit blocks and multiple levels of conductors are used to distribute power and signals from off the IC to the circuit blocks within the IC, between the circuit blocks, and between cells within each circuit block.
"It is well known that the conductors can be formed by lithographically patterning a layer of conductive material to form conductive lines as viewed from above the IC substrate. The conductive layers with conductive lines formed therein are isolated by an insulating layer so that lines of one layer which cross another layer do not physically or electrically contact each other. When it is desired to electrically couple a conductive line formed in one layer to a conductive line formed in another layer, a conductive via can be formed extending through the insulating layer between the two conductors.
"Typically, the topmost two or three levels of the interconnection metal layers are used for power and ground routing in an integrated circuit chip. Taking a 1P7M interconnection scheme for example, the topmost level of the interconnection metal layers, i.e., metal-7 or M7, and M6, i.e., the metal layer that is one level lower than M7, are both used to constitute a power/ground mesh-like network. In some cases, the aforesaid M7 metal layer may be a redistribution layer (RDL) and part of the M5 metal layer may also be used to form the power/ground mesh-like network.
"FIG. 1 is a schematic, partial plan view showing a conventional power/ground mesh interconnection network and bumping sites in an IC chip having six levels of metal layers. The mesh interconnection network 20 consists of a plurality of horizontal power (V.sub.DD) lines 22a and ground (V.sub.SS) lines 22b, which may be fabricated in the RDL, and longitudinal power lines 24a and ground lines 24b, which may be fabricated in M6. The horizontal power lines 22a and ground lines 22b are parallel to one another. The longitudinal power lines 24a and ground lines 24b are parallel to one another. The horizontal power lines 22a and ground lines 22b are substantially orthogonal to the underlying power lines 24a and ground lines 24b. The V.sub.DD bumping sites and V.sub.SS bumping sites are disposed in a staggered manner. Through the mesh interconnection network 20 and respective via stacks (not shown), the power or ground signals are provided from respective power or ground rings to the cell level devices such as transistors or regions which are fabricated in or on the main surface of a semiconductor substrate (not shown) and are not equally spaced from the ring.
"However, the prior approach induces high voltage drop (or IR drop), which results in increased power consumption and reduced signal timing speed. Besides, the conventional power/ground mesh-like network in the topmost two or three levels of the interconnection metal layers significantly limits the routing space for signal line in a chip. Therefore, there is a strong need in this industry to provide an improved power and ground routing for the integrated circuit chip that is capable of reducing the metal layer resistance, thus lowering the IR drop over a chip and improving the chip performance, and providing more space for signal routing."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "It is one object of the invention to provide an improved power and ground routing scheme for the integrated circuit (IC) chips that is capable of reducing the IR drop and/or providing more space for signal routing.
"According to one aspect of this invention, an integrated circuit chip includes a semiconductor substrate; a power/ground interconnection network in a topmost metal layer over the semiconductor substrate; and at least a bump pad on/over the power/ground interconnection network. The power/ground interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.
"According to another aspect of this invention, an integrated circuit chip includes a semiconductor substrate; a bump pad on or over a topmost metal layer on the semiconductor substrate; a first power/ground line in the topmost metal layer, connected to the bump pad and extending along a first direction; and at least an extension portion in the topmost metal layer, connected to the bump pad and extending along a second direction.
"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings."
For additional information on this patent, see: Lin, Chih-Ching; Chang, Ya-Ting; Chuang, Chia-Lin. Integrated Circuit Chip with Reduced IR Drop. U.S. Patent Number 8772928, filed
Keywords for this news article include: Electronics,
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