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Patent Issued for Impedance Calibration Circuit, Semiconductor Memory Device with the Impedance Calibration Circuit and Layout Method of Internal...

July 23, 2014



Patent Issued for Impedance Calibration Circuit, Semiconductor Memory Device with the Impedance Calibration Circuit and Layout Method of Internal Resistance in the Impedance Calibration Circuit

By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Moon, In Jun (Chungcheongbuk-do, KR), filed on March 11, 2011, was published online on July 8, 2014.

The assignee for this patent, patent number 8773161, is Hynix Semiconductor Inc. (Kyoungki-do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to a semiconductor memory device, and more particularly, to an impedance calibration circuit for impedance matching between a semiconductor memory device and an external device, a semiconductor memory device including the impedance calibration circuit at an input/output terminal thereof, and a layout method of an internal resistance in the impedance calibration circuit.

"Typically, a high speed semiconductor memory device such as a DDR3 is provided with an impedance calibration circuit that calibrates an on die termination (ODT) value in response to process, voltage, and temperature (PVT) variation.

"The impedance calibration circuit calibrates the impedance of an internal resistance by utilizing a resistance connected to the outside of the memory chip and provides a code signal having the calibrated information to a data input/output (I/O) driver. Then, the driving level of the data I/O driver is adjusted using the code signal and impedance matching with an external device that interfaces data is thereby completed.

"The impedance calibration circuit includes a driver provided with a plurality of legs in order to calibrate the impedance of the internal resistance, and the code signal having the impedance calibration information is generated and outputted by comparing the impedance of the legs to the impedance of the external resistance.

"The data I/O driver also includes a plurality of legs for adjusting the driving force in response to the code signal. The impedance corresponding to the data outputted to outside the memory device is calibrated as the impedance of the legs varies in response to the code signal.

"However, the structure of conventional semiconductor memory devices tends to cause an impedance mismatch between the impedance calibration circuit and the data I/O driver. It is difficult to detect and calibrate for this impedance mismatch, and therefore the generated impedance mismatch can be problematic.

"Specifically, in a conventional data I/O driver, the legs have various resistance values in order to support various internal resistance modes. To the contrary, a conventional impedance calibration circuit only includes legs for comparison with an external resistance. That is, unlike the data I/O driver, the legs of the conventional impedance calibration circuit have only a single resistance value, with the single resistance value being the same resistance value as the external resistance.

"Therefore, in a conventional semiconductor memory device there is a high probability that an impedance mismatch will occur, since the legs of the impedance calibration circuit and the legs of the data I/O driver have different layout structures.

"Additionally, both the conventional impedance calibration circuit and the conventional data I/O driver include a pull-up driver and a pull-down driver. The pull-up driver of the impedance calibration circuit is connected to a pin of the external resistance. The pull-down driver of the impedance calibration circuit is not directly connected to the pin of the external resistance, and is instead connected to the pull-up driver through an internal node. To the contrary, in a conventional data I/O driver, the pull-up driver and pull-down driver are both connected to an external data input/output pin.

"The difference in the pull-up and pull-down drivers of the conventional data I/O driver and the conventional impedance calibration circuit are another example of a differing structure that causes a problem. The difference in structure of the connection to an external pin of the driver of the impedance calibration circuit and the data I/O driver results in a high probability that an impedance mismatch will be generated.

"To summarize, an impedance mismatch is generated between the impedance calibration circuit and the data I/O driver of the conventional device due to the difference in layout structure and connection between the impedance calibration circuit and the data I/O driver.

"This impedance mismatch is problematic, in that an impedance calibration value DQ_CAL may differ significantly from a target value TARGET upon pull-down driving of the data I/O driver. This difference is shown in illustration (a) of FIG. 1.

"For reference, in illustration (a) and (b) of FIG. 1, `ZQ` indicates the impedance of the impedance calibration circuit before the impedance calibration, `ZQ_CAL` indicates the impedance of the impedance calibration circuit after the impedance calibration, and `DQ` indicates impedance of the data I/O driver before the impedance calibration.

"In requires much time and effort to fix the calibration problem caused by the conventional impedance calibration circuit which includes legs having only a single resistance value and which calibrates the impedance by comparing these legs only to an external resistance."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Embodiments of the present invention include an impedance calibration circuit that can easily adjust impedance so that the impedance matches the impedance of a data I/O driver.

"Additionally, embodiments of the present invention include a semiconductor memory device that can easily calibrate an impedance mismatch occurring between a data I/O driver and an impedance calibration circuit.

"Further, embodiments of the present invention include a method of laying out an internal resistance of an impedance calibration circuit that can easily calibrate the impedance of a resistance provided within the impedance calibration circuit.

"In one aspect of the present invention, an impedance calibration circuit includes a driving circuit including internal resistances, at least one thereof being a variable resistance. The driving circuit compares the impedance of the internal resistances to the input/output impedance of an external device and provides the result as a calibrated voltage. A comparing circuit compares the calibrated voltage to a reference voltage and provides a code signal for the impedance calibration with the external device.

"The variable resistance may include a metal line having a passage extending between both ends thereof, and a metal option having a connection structure that shortens the passage.

"Alternatively, the variable resistance may include resistance elements having a parallel structure and switching elements that control the parallel connection between the resistance elements. The resistance value of the variable resistance is varied by selectively connecting the respective switching elements.

"Preferably, each switching element corresponds to a metal option selectively connected between the resistance elements.

"Preferably, the plurality of the internal resistances are connected in parallel to an external resistance corresponding to the input/output impedance of an external device, and the plurality of the internal resistances (except for the variable resistance) have resistance values that have a predetermined proportional relationship with one another.

"Preferably, the plurality of the internal resistances (except for the variable resistance has resistance values that are in a proportional relationship of 1:1 with one another.

"According to another aspect of the present invention, a semiconductor memory device includes an impedance calibration circuit including internal resistances, at least one thereof being a variable resistance, and comparing the impedance of the internal resistances to the input/output impedance of an external device and providing a code signal; and a data input/output driver driving data and calibrating, in response to the code signal, an impedance corresponding to the data so that the impedance corresponds to the input/output impedance of the external device.

"Preferably, the impedance calibration circuit adjusts a code value of the code signal through the comparison of the impedance of the internal resistances and the input/output impedance of the external device, and the impedance of the internal resistances is adjusted by the code value of the code signal.

"Preferably, the variable resistance has a resistance value that is varied independently of the impedance determined following the code value of the code signal.

"Preferably, the impedance calibration circuit includes a driving circuit including the internal resistances, at least one thereof being the variable resistance, and comparing the impedance of the internal resistances and the input/output impedance of the external device and providing the result as a calibration voltage; and a comparing circuit comparing the calibration voltage to a reference voltage and providing the code signal.

"Preferably, the driving circuit includes driving devices each providing a predetermined voltage in response to the code signal; constant resistances are respectively connected in correspondence to some of the driving devices between a node to which the predetermined voltage is provided and a node to which the calibration voltage is provided; and at least one variable resistance is connected in correspondence to the remaining driving devices other than the driving devices to which the constant resistances are connected between a node to which the predetermined voltage is provided and a node to which the calibration voltage is provided.

"The variable resistance may include a metal line having a passage extending between both ends thereof, and a metal option having a connection structure that shortens the passage.

"Alternatively, the variable resistance includes resistance elements having a parallel structure and switching elements that control the parallel connection between the resistance elements, and the resistance value of the variable resistance is varied by selective connections of respective switching elements.

"Preferably, each switching element corresponds to the metal option selectively connected between the resistance elements.

"Preferably, the constant resistances have resistance values that are in a predetermined proportional relationship with one another.

"Preferably, the constant resistances have resistance values that are in a proportional relationship of 1:1 with one another.

"Preferably, the data input/output driver includes resistances that vary the impedance corresponding to the data in response to the code signal, and the resistances include constant resistances and at least one variable resistance.

"According to another aspect of the present invention, a method of laying out internal resistance in an impedance calibration circuit, in which a plurality of internal resistances for impedance matching between a semiconductor memory device and an external device is laid out in an impedance calibration circuit provided in the semiconductor memory device, includes laying out at least one of the plurality of internal such that it includes a metal line having a passage extended between both ends thereof; and at least one metal option having a connection structure that shortens the extended passage of the metal line, wherein the resistance value is varied following whether the metal option is cut or not.

"The metal line may have at least one bended portion and form a closed passage by the bended portion and the metal option.

"Alternatively, the metal line is formed via two or more layers so as to have at least one bended portion.

"Preferably, the metal line includes a plurality of resistance elements respectively formed through the two or more layers and electrically connected with each other, and the metal option is connected between the resistance elements.

"The present invention provides an impedance calibration circuit including internal resistances having at least one variable resistance. Therefore, it is possible to easily calibrate impedance mismatch between the impedance calibration circuit and a data I/O driver.

"Also, the present invention provides a semiconductor memory device in which at least one of the internal resistances of an impedance calibration circuit is a variable resistance. Therefore, it is possible to easily calibrate impedance mismatch between the impedance calibration circuit and a data I/O driver.

"Also, the present invention provides a method of laying out internal resistance in an impedance calibration circuit in which a resistance value of at least one of the internal resistances provided in an impedance calibration circuit is variable. Therefore, it is possible to easily calibrate impedance mismatch between the impedance calibration circuit and a data I/O driver."

For more information, see this patent: Moon, In Jun. Impedance Calibration Circuit, Semiconductor Memory Device with the Impedance Calibration Circuit and Layout Method of Internal Resistance in the Impedance Calibration Circuit. U.S. Patent Number 8773161, filed March 11, 2011, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8773161.PN.&OS=PN/8773161RS=PN/8773161

Keywords for this news article include: Electronics, Hynix Semiconductor Inc..

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Source: Electronics Newsweekly


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