News Column

Patent Issued for Image Sensor and Camera System Having the Same

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Samsung Electronics Co., Ltd. (Suwon-Si, KR) has been issued patent number 8773544, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Koh, Kyoung-Min (Hwaseong-si, KR); Ham, Seog-Heon (Suwon-si, KR); Lim, Yong (Hwaseong-si, KR).

This patent was filed on December 6, 2011 and was published online on July 8, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Exemplary embodiments relate to an image sensor, and more particularly to an image sensor having high sensitivity and high signal to noise ratio (SNR) without degrading frame rate, and a camera system including the image sensor.

"Camera systems require a high speed operation in a video recording mode compared to a still image capturing mode. Therefore, an exposure time of camera systems in a video recording mode is shorter than an exposure time of camera systems in a still image capturing mode. For this reason, a high sensitivity image sensor that is able to sufficiently detect incident light during a short exposure time is required for a video recording.

"Usually, digital still cameras use a relatively low sensitivity image sensor as compared to camcorders, which are mainly used for video recording. Therefore, a quality of a video image generated by digital still cameras in a video recording mode is relatively low."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Exemplary embodiments are directed to providing an image sensor having high sensitivity and high signal to noise ratio (SNR) without degrading frame rate.

"Exemplary embodiments are also directed to providing a camera system that includes the image sensor having high sensitivity and high signal to noise ratio (SNR) without degrading frame rate.

"According to an aspect of the exemplary embodiments, an image sensor includes a pixel array, a reference voltage generation unit, an analog-digital conversion unit, and a control unit. The pixel array includes a plurality of pixels arranged columns and rows, where each of the pixels detects incident light and generates an analog signal in response to the detected incident light. The reference voltage generation unit generates a reference voltage that changes at a constant rate in a first operation mode and alternately decreases and increases at the constant rate in a second operation mode. The analog-digital conversion unit converts the analog signal to a digital value a first number of times using the reference voltage and generates a digital signal by summing the first number of the digital values, where the first number corresponds to a total number of decrease and increase of the reference voltage and the analog-digital conversion unit operates at a same speed both in the first operation mode and in the second operation mode to generate the digital signal. The control unit controls operations of the pixel array, the reference voltage generation unit, and the analog-digital conversion unit.

"In the exemplary embodiments, the first operation mode may be a still image capturing mode and the second operation mode may be a video recording mode.

"In the exemplary embodiments, the reference voltage generation unit may receive a mode signal, a gain signal, and a count enable signal from the control unit, generate the reference voltage that decreases at the constant rate during an active period, in which the count enable signal is enabled, when the mode signal is at a first level corresponding to the first operation mode, and generate the reference voltage that alternately decreases and increases at the constant rate in a cycle of a sub period, which is a portion of the active period divided by a value of the gain signal, when the mode signal is at a second level corresponding to the second operation mode.

"In the exemplary embodiments, the reference voltage generation unit may include a resistor connected to a supply voltage and a current generation unit coupled between the resistor and a ground voltage, where the current generation unit receives a mode signal, a gain signal, and a count enable signal from the control unit, generates a reference current that increases at the constant rate during an active period, in which the count enable signal is enabled, when the mode signal is at a first level corresponding to the first operation mode, and generates the reference current that alternately increases and decreases at the constant rate in a cycle of a sub period, which divides the active period with a value of the gain signal, when the mode signal is at a second level corresponding to the second operation mode. The reference current may flow from the resistor to the ground voltage. The reference voltage generation unit may output the reference voltage from a node at which the resistor and the current generation unit is coupled.

"In the exemplary embodiments, each of the pixels may consecutively generate a first analog signal corresponding to a reset component and a second analog signal corresponding to the detected incident light, and the analog-digital conversion unit may generate the digital signal corresponding to an effective intensity of incident light among the detected incident light by performing a correlated double sampling (CDS) operation on the first analog signal and the second analog signal.

"The analog-digital conversion unit may include a plurality of comparators, each of which is connected to a corresponding column of the pixel array and generates a comparison signal by comparing the first analog signal with the reference voltage and comparing the second analog signal with the reference voltage, and a plurality of counters, each of which is connected to a corresponding comparator and receives the comparison signal from the corresponding comparator, where each of the counters receives a count clock signal and an up-down control signal from the control unit and generates the digital signal by performing one of a down-counting and an up-counting in response to the up-down control signal in synchronization with the count clock signal while the comparison signal is enabled.

"The control unit may provide the plurality of the counters with the count clock signal having a same frequency in the first operation mode and in the second operation mode.

"Each of the counters may generate a first counting value by accumulatively performing the down-counting the first number of times from zero when each of the counters receives the first analog signal from the pixel array, and generate a second counting value by accumulatively performing the up-counting the first number of times from the first counting value when each of the counters receives the second analog signal from the pixel array, where each of the counters outputs the second counting value as the digital signal.

"The analog-digital conversion unit may perform a binning operation on neighboring pixels of a same color in the second operation mode.

"The analog-digital conversion unit may perform a two-by-two (2*2) binning operation on four neighboring pixels of the same color that are adjacent in a column direction and in a row direction of each other in the second operation mode.

"The control unit may consecutively select rows, which are included in the pixel array, having pixels on which the binning operation is performed in the second operation mode.

"Each of the counters may accumulatively perform the down-counting and the up-counting for the rows having pixels on which the binning operation is performed in the second operation mode.

"The analog-digital conversion unit may further include a plurality of adders, each of which generates a binning digital signal by summing the digital signals generated by counters which correspond to pixels on which binning operation is performed in the second operation mode.

"The control unit may include a column driver that consecutively outputs the digital signals received from the plurality of the counters in the first operation mode and consecutively outputs the binning digital signals received from the plurality of the adders in the second operation mode.

"According to an aspect of the exemplary embodiments, a camera system includes an image sensor, a storage unit, and a processor. The image sensor generates a digital signal corresponding to incident light. The storage unit stores the digital signal. The processor controls operations of the image sensor and the storage unit. The image sensor includes a pixel array, a reference voltage generation unit, an analog-digital conversion unit, and a control unit. The pixel array includes a plurality of pixels arranged columns and rows, where each of the pixels detects incident light and generates an analog signal in response to the detected incident light. The reference voltage generation unit generates a reference voltage that consistently changes at a constant rate in a first operation mode and generates the reference voltage that alternately decreases and increases at the constant rate in a second operation mode. The analog-digital conversion unit converts the analog signal to a digital value a first number of times using the reference voltage and generates the digital signal by summing the first number of the digital values, where the first number corresponds to a total number of decrease and increase of the reference voltage and the analog-digital conversion unit operates in a same speed both in the first operation mode and in the second operation mode to generate the digital signal. The control unit controls operations of the pixel array, the reference voltage generation unit, and the analog-digital conversion unit."

For the URL and additional information on this patent, see: Koh, Kyoung-Min; Ham, Seog-Heon; Lim, Yong. Image Sensor and Camera System Having the Same. U.S. Patent Number 8773544, filed December 6, 2011, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8773544.PN.&OS=PN/8773544RS=PN/8773544

Keywords for this news article include: Samsung Electronics Co. Ltd.

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Source: Electronics Newsweekly


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