The patent's inventors are Cheng, Kangguo (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to forming improved back gate field effect transistor (FET) devices by using shallow trench isolation (STI) regions to introduce back gate dopant material.
"Semiconductor-on-insulator (SOI) devices, such as silicon-on-insulator devices, offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of latch up, which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
"On the other hand, SOI devices generally suffer from floating body effects. The body of an SOI FET stores electrical charge as a function of the history of the device, thus changing the body voltage accordingly and becoming a 'floating' body. As such, an SOI FET has threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-threshold voltage (sub-Vt) leakage and threshold voltage (Vt) mismatch among geometrically identical adjacent devices. Floating body effects in an SOI field effect transistor are particularly a concern in static random access memory (SRAM) cells, where Vt matching is extremely important as operating voltages continue to be scaled down.
"An evolution beyond the standard FET (which has a single top gate that controls the FET channel) is the double-gated FET, in which the channel is confined between a top and a bottom gate. Positioning the channel between a top gate and a bottom gate allows for control of the channel by the two gates from both sides of the channel, reducing short channel effects. Further, a double-gated FET may exhibit higher transconductance and reduced parasitic capacitance as compared to a single-gated FET. The presence of the back gate allows for enhanced on-chip power management and device tuning. Multiple threshold voltage (Vt) devices may also be achieved on a single IC chip by applying different back biases at the back gates of various devices."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "In an exemplary embodiment, a method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants.
"In another embodiment, a method of forming a back gate transistor device includes forming a protective pad layer over a semiconductor-on-insulator (SOI) substrate, the SOI substrate having a bulk substrate layer, a buried insulator (BOX) layer formed on the bulk substrate layer, and an active SOI layer formed on the buried insulator layer; forming an open isolation trench through the protective pad layer, the active SOI layer, the BOX layer, and into a portion of the bulk substrate layer; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench and the BOX layer, such that the doped well region serves as a back gate conductor, wherein the sidewall spacers prevent contamination of the BOX layer and the active SOI layer device by dopants.
"In another embodiment, a back gate transistor device includes a semiconductor-on-insulator (SOI) substrate, the SOI substrate having a bulk substrate layer, a buried insulator (BOX) layer formed on the bulk substrate layer, and an active SOI layer formed on the buried insulator layer; an isolation trench formed through the active SOI layer, the BOX layer, and into a portion of the bulk substrate layer; sidewall spacers formed in the open isolation trench; at least a portion of the isolation trench filled with a dopant source insulator material; and a doped well region disposed below a bottom surface of the isolation trench and the BOX layer, the doped well region configured as a back gate conductor, wherein dopants from the doped well region originate from the dopant source insulator material."
For the URL and additional information on this patent, see: Cheng, Kangguo; Doris, Bruce B.; Khakifirooz, Ali; Shahidi, Ghavam G.. Field Effect Transistor Devices with Dopant Free Channels and Back Gates. U.S. Patent Number 8772143, filed
Keywords for this news article include: Electronics, Semiconductor,
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