News Column

Patent Issued for Electronic Device Submounts Including Substrates with Thermally Conductive Vias

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Cree, Inc. (Durham, NC) has been issued patent number 8772817, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Yao, Zhimin Jamie (Santa Barbara, CA).

This patent was filed on December 22, 2010 and was published online on July 8, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to the packaging of semiconductor devices, and more particularly to submounts for use in packaging semiconductor devices, such as light emitting diodes.

"Light emitting diodes (LEDs) are often packaged within leadframe packages. A leadframe package typically includes a molded plastic body which encapsulates an LED, a lens portion, and thin metal leads connected to the LED and extending outside the plastic body. The metal leads of the leadframe package serve as the conduit to supply the LED with electrical power and, at the same time, may act to draw heat away from the LED. Heat is generated by the LED when power is applied to the LED to produce light. A portion of the leads extends out from the package body for connection to circuits external to the leadframe package.

"Some of the heat generated by the LED is dissipated by the plastic package body; however, most of the heat is drawn away from the LED via the metal components of the package. The metal leads are typically very thin and have a small cross section. For this reason, capacity of the metal leads to remove heat from the LED is limited. This limits the amount of power that can be applied to the LED thereby limiting the amount of light that can be generated by the LED.

"To increase the capacity of an LED package to dissipate heat, in one LED package design, a heat sink slug is placed under the metal leads within the LED package. The heat sink slug increases the capacity of the LED package to dissipate heat; however, the heat sink slug increases the size, the mass, and the cost of the LED package. Increases in the size, the mass, and the cost are undesirable.

"In another LED package design, the leads of the leadframe are extended (in various shapes and configurations) beyond the immediate edge of the LED package body. This increases the surface area of the portions of the leads exposed to the surrounding air. The increased exposed surface area of the extended leads increases the capacity of the LED package to dissipate heat; however, the extended leads increase the size, the mass, and the cost of the LED package.

"Another undesirable aspect of the leadframe package design relates to problems associated with thermal expansion of the package. When heat is generated, the LED package experiences thermal expansion. Each of the parts of the LED package has a different coefficient of thermal expansion (CTE). For example, the CTE of the LED, the CTE of the package body, the CTE of the leads, and the CTE of lens are different from each other. For this reason, when heated, each of these parts experience different degrees of thermal expansion resulting in mechanical stresses between the parts of the package thereby adversely affecting its reliability.

"To avoid some of the problems associated with leadframe based packages, solid state electronic devices can be mounted on submounts that provide mechanical support, electrical connection, and thermal dissipation, as well as other functionality, for the electronic devices. For example, solid state light sources, such as semiconductor light emitting diodes, can be mounted on submounts as disclosed in U.S. Pre-grant Publication No. 2007/0253209 which is assigned to the assignee of the present invention and which is incorporated herein by reference as if fully set forth herein. The submounts may further be provided in packages that provide protection, color selection, focusing and the like for light emitted by the light emitting device. A solid state light emitting device may be, for example, an organic or inorganic light emitting diode ('LED'). Some packages for light emitting diodes are described in U.S. Pre-grant Publication Nos. 2004/0079957, 2004/0126913, and 2005/0269587 which are assigned to the assignee of the present invention, and which are incorporated herein by reference as if set forth fully herein.

"A ceramic-based submount is illustrated in FIG. 1. As shown therein, a submount 5 for mounting an electronic device can be formed by punching or drilling via holes 12 in a substrate of green state alumina 10. As used herein, 'substrate' refers to a layer of material that provides mechanical support for an object, such as an electronic device. A submount includes a substrate and therefore provides mechanical support for an electronic device as well, but a submount may also include features that provide electrical connections such as die attach pads, electrical traces, etc., features that dissipate thermal energy, features that provide optical functionality, such as reflectors and/or lenses, and/or other functionality. The via holes 12 can be plated and/or filled with conductive material 14, such as copper or aluminum, and the green state alumina tape 10 and the vias 12, 14 can be co-fired to transform the green state alumina tape 10 into an alumina substrate 10. Contact pads 16, 18, that electrically connect to the vias 12, 14, can be formed on opposite sides of the alumina substrate 10, for example by plating and patterning metal traces. In this manner, electrically and thermally conductive paths can be formed from one side of the substrate to the other."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "Some embodiments provide a submount for an electronic device. The submount includes a substrate including first and second major surfaces on opposite sides of the substrate, a surface insulating layer on the first major surface of the semiconductor substrate, and a die attach pad on the surface insulating layer. The die attach pad may be electrically insulated from the semiconductor substrate by the surface insulating layer. The submount further includes a heatsink pad on the second major surface of the substrate, and a thermal conduction member extending from the second major surface of the substrate through the substrate toward the first major surface of the substrate. The thermal conduction member may be between the die attach pad and the heatsink pad, and the thermal conduction member may have a higher thermal conductivity than a thermal conductivity of the substrate.

"The submount may further include an electrically insulating sidewall spacer between the thermal conduction member and the substrate. The thermal conduction member may be insulated from the substrate by the electrically insulating sidewall spacer.

"The thermal conduction member may be in direct contact with the surface insulating layer and may be insulated from the die attach pad by the surface insulating layer.

"The thermal conduction member may be in direct contact with the heatsink pad.

"The submount may further include a second surface insulating layer on the second major surface of the substrate. The second surface insulating layer may be between the heatsink pad and the substrate. The thermal conduction member may extend through the second surface insulating layer to contact the heatsink pad.

"The thermal conduction member may be electrically isolated from the heatsink pad by the second surface insulating layer.

"The submount may further include a plurality of thermal conduction members extending from the second major surface of the substrate toward the first major surface of the substrate.

"The submount may further include a second surface insulating layer on the second major surface of the substrate, and the second surface insulating layer may be between the heatsink pad and the substrate.

"The plurality of thermal conduction members may extend through the second surface insulating layer to contact the heatsink pad.

"The plurality of thermal conduction members may be electrically isolated from the heatsink pad by the second surface insulating layer.

"The plurality of thermal conduction members may include planar surfaces that are parallel to corresponding planar surfaces of adjacent ones of the thermal conduction members.

"The submount may further include a second surface insulating layer on the second major surface of the substrate, and a contact pad on the second major surface of the substrate. The contact pad may be electrically isolated from the substrate by the second surface insulating layer. The submount may further include a thermal conduction member extending through the substrate, the first surface insulating layer and the second surface insulating layer. The thermal conduction member may electrically connect the die attach pad and the contact pad in some embodiments.

"The thermal conduction member may be insulated from the substrate by an electrically insulating sidewall spacer.

"The submount may further include a bonding pad on the first major surface of the substrate. The bonding pad may be electrically insulated from the substrate by the first surface insulating layer. The submount may further include a second contact pad on the second major surface of the substrate. The second contact pad may be electrically isolated from the substrate by the second surface insulating layer. A second thermal conduction member may extend through the substrate, the first surface insulating layer and the second surface insulating layer. The second thermal conduction member may electrically connect the bonding pad and the second contact pad.

"The thermal conduction member may be insulated from the substrate by a first electrically insulating sidewall spacer and the second electrically conductive thermal conduction member may be insulated from the substrate by a second electrically insulating sidewall spacer.

"Some embodiments provide methods of forming a submount for an electronic device. The methods may include providing a substrate including first and second major surfaces on opposite sides of the substrate, forming a surface insulating layer on the first major surface of the semiconductor substrate, forming a die attach pad on the surface insulating layer, wherein the die attach pad is electrically insulated from the semiconductor substrate by the surface insulating layer, forming a heatsink pad on the second major surface of the substrate, and forming a thermal conduction member extending from the second major surface of the substrate through the substrate toward the first major surface of the substrate. The thermal conduction member may be between the die attach pad and the heatsink pad, and the thermal conduction member may have a higher thermal conductivity than a thermal conductivity of the substrate.

"The methods may further include forming an electrically insulating sidewall spacer between the thermal conduction member and the substrate, wherein the thermal conduction member may be insulated from the substrate by the electrically insulating sidewall spacer.

"The thermal conduction member may be in direct contact with the surface insulating layer and may be insulated from the die attach pad by the surface insulating layer.

"The thermal conduction member may be in direct contact with the heatsink pad.

"The methods may further include forming a second surface insulating layer on the second major surface of the substrate. The second surface insulating layer may be between the heatsink pad and the substrate.

"The thermal conduction member may extend through the second surface insulating layer to contact the heatsink pad.

"The thermal conduction member may be electrically isolated from the heatsink pad by the second surface insulating layer.

"The methods may further include forming a plurality of thermal conduction members extending from the second major surface of the substrate toward the first major surface of the substrate.

"The methods may further include forming a second surface insulating layer on the second major surface of the substrate. The second surface insulating layer may be between the heatsink pad and the substrate.

"Methods of forming submount for an electronic device according to further embodiments include providing a substrate including first and second major surfaces on opposite sides of the substrate,

"forming a via hole through the substrate from the first major surface to the second major surface of the substrate,

"forming an electrically insulating sidewall spacer in the via hole, and forming a thermal conduction member within the via hole. The thermal conduction member may have a higher thermal conductivity than a thermal conductivity of the substrate, and the thermal conduction member may be insulated from the substrate by the electrically insulating sidewall spacer. The methods may further include forming a surface insulating layer on the first major surface of the substrate to cover the thermal conduction member.

"A light emitting device according to some embodiments includes a submount and a solid state light emitting device on the submount. The submount includes a substrate including first and second major surfaces on opposite sides of the substrate, a surface insulating layer on the first major surface of the semiconductor substrate, and a die attach pad on the surface insulating layer. The die attach pad may be electrically insulated from the semiconductor substrate by the surface insulating layer. The submount further includes a heatsink pad on the second major surface of the substrate, and a thermal conduction member extending from the second major surface of the substrate through the substrate toward the first major surface of the substrate. The thermal conduction member may be between the die attach pad and the heatsink pad, and the thermal conduction member may have a higher thermal conductivity than a thermal conductivity of the substrate. The solid state light emitting device is mounted on the die attach pad."

For the URL and additional information on this patent, see: Yao, Zhimin Jamie. Electronic Device Submounts Including Substrates with Thermally Conductive Vias. U.S. Patent Number 8772817, filed December 22, 2010, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772817.PN.&OS=PN/8772817RS=PN/8772817

Keywords for this news article include: Cree Inc., Electronics, Semiconductor, Light-emitting Diode.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters