Patent number 8775897 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Various data processing systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In each of the systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. As information is stored or transmitted in the form of digital data, errors may be introduced that, if not corrected, can corrupt the data and render the information unusable. The effectiveness of any transfer is impacted by any losses in data caused by various factors. Many types of data processors have been developed to detect and correct errors in digital data. For example, data decoders such as Low Density Parity Check (LDPC) decoders may be used to decode the values of data bits or multi-bit symbols retrieved from storage or transmission systems.
"Some LDPC data decoders implement error correction techniques such as bit or symbol flipping. In such decoders, if conventional data decoding fails to determine the correct data values and satisfy parity checks, the value of some bits or symbols in a block of data may be changed or flipped during a decoding process in an attempt to determine the correct data values. However, bit or symbol flipping may result in output data that is still incorrect despite satisfying parity checks in the decoder.
"A need therefore remains for a data processing system with improved error detection and correction."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed having a data processing circuit that processes an input data block in sections, generating at least one possible section result for each of the sections of the input data block, and in some embodiments providing multiple possible results for at least one of the sections. A number of possible results for the input data block can be generated by combining different versions of each of the section results. The possible results for the input data block are checked for errors in an error detection circuit to determine which, if any, of the possible results is correct and error-free. In some embodiments, the input data block comprises a data sector read from a magnetic hard disk or received from a transmission medium, the section results comprise hard decisions for component codewords of the data sector, the results comprise hard decisions for the data sector made up of hard decisions for each of the component codewords of the data sector, and the data processing system yields as output at least the result that passes the error check. In some instances of the aforementioned embodiments, the data processing circuit is an LDPC decoder and the error detection circuit is a cyclic redundancy check (CRC) circuit.
"This summary provides only a general outline of some embodiments according to the present invention. Many other objects, features, advantages and other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings."
URL and more information on this patent, see: Wang, Chung-Li; Chen, Lei; Zhang, Fan; Yang, Shaohua; Yen, Johnson. Data Processing System with Failure Recovery. U.S. Patent Number 8775897, filed
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