News Column

Patent Issued for Chip Structure Having Redistribution Layer

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Hsu, Hung-Yuan (Taichung, TW); Kao, Sui-An (Taichung, TW), filed on January 12, 2012, was published online on July 8, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8772922 is assigned to Siliconware Precision Industries Co., Ltd. (Taichung, TW).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to chip structures and fabrication methods thereof, and more particularly, to a chip structure having a redistribution layer and a fabrication method thereof.

"Along with the development of electronic industries, electronic products have a trend towards multi-function and high performance. Currently, packaging substrates for carrying semiconductor chips can be such as wire bonding packaging substrates, chip scale packaging (CSP) substrates, flip chip ball grid array (FCBGA) packaging substrates and so on. To meet operational demands of microprocessors, chipsets and graphic chips, it is necessary to improve functions of the packaging substrates in chip signal transmission, improving bandwidth and controlling impedance so as to meet the development of packages with high I/O count.

"Conventionally, a semiconductor chip with a plurality of electrode pads on a surface thereof is disposed to a packaging substrate with a plurality of conductive pads corresponding to the electrode pads, and a plurality of conductive bumps or other conductive adhesive material or gold wires are disposed between the semiconductor chip and the packaging substrate so as to electrically connect the semiconductor chip to the packaging substrate.

"Further, a plurality of semiconductor packages can be stacked together to meet requirements for multi-function and high operating efficiency. In addition, redistribution layer (RDL) technology can be used to effectively utilize chip area so as to improve performance.

"For example, U.S. Pat. No. 7,170,160 discloses a chip structure having a redistribution layer, wherein a plurality of chips is stacked together and electrically connected to each other through bonding wires.

"FIG. 1A is an upper view of the chip structure as disclosed by U.S. Pat. No. 7,170,160, and FIG. 1B is a cross-sectional view of the chip structure. Referring to FIGS. 1A and 1B, a chip 10 with a plurality of electrode pads 11 disposed on a surface thereof is provided; a first passivation layer 12a is formed to cover the chip 10 and the electrode pads 11, and a plurality of first openings 120a is formed in the first passivation layer 12a for exposing the electrode pads 11, respectively; a redistribution layer 13 is formed on the first passivation layer 12a and conductive vias 130 are formed in the first openings 120a for electrically connecting to the electrode pads 11, respectively, wherein the redistribution layer 13 has a plurality of conductive pads 131 and widened portions 132, the widened portions 132 being used for improving the electrical performance of the structure; further, a second passivation layer 12b is formed to cover the first passivation layer 12a and the redistribution layer 13 and has a plurality of second openings 120b for exposing the conductive pads 131, respectively.

"However, since the widened portions 132 having a large area are made of a metal material while the first passivation layer 12a or the second passivation layer 12b is made of a non-metal material, the bonding between the widened portion 132 and the second passivation layer 12b is quite poor, which easily results in delamination of the widened portions 132 from the second passivation layer 12b and thus reduces the quality of the electrical connection.

"Therefore, it is imperative to provide a chip structure having a redistribution layer and a fabrication method thereof so as to overcome the above-described drawback."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Accordingly, the present invention provides a chip structure having a redistribution layer and a fabrication method thereof so as to prevent delamination of a widened portion of a redistribution layer from a second passivation layer.

"In order to achieve the above and other objects, the present invention provides a chip structure having a redistribution layer, which comprises: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; a first passivation layer formed on the active surface and the electrode pads and having a plurality of first openings for exposing the electrode pads, respectively; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units comprises a conductive pad, a conductive via formed in one of the first openings and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer formed on the first passivation layer and the redistribution layer and filled in the at least a first through opening of the conductive trace of each of the wiring units and having a plurality of second openings for exposing the conductive pad of each of the wiring units.

"Therein, the redistribution layer can be comprised of a seed layer and a metal layer disposed in sequence.

"The present invention further provides a fabrication method of a chip structure having a redistribution layer, which comprises the steps of: providing a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; forming a first passivation layer on the active surface and the electrode pads and forming in the first passivation layer a plurality of first openings for exposing the electrode pads, respectively; forming a redistribution layer on the first passivation layer, wherein the redistribution layer has a plurality of wiring units, each of which comprises a conductive pad, a conductive via formed in one of the first openings and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and forming a second passivation layer to cover the first passivation layer and the redistribution layer and filling the second passivation layer in the at least a first through opening of the conductive trace of each of the wiring units and forming a plurality of second openings in the second passivation layer for exposing the conductive pad of each of the wiring units.

"In the above-described method, the step of forming the redistribution layer can further comprise the steps of: forming a seed layer on the first passivation layer, on the walls of the first openings and on the electrode pads in the first openings; forming a photoresist layer on the seed layer and forming a plurality of openings in the photoresist layer to expose portions of the seed layer; forming a metal layer on the seed layer in the openings of the photoresist layer; and removing the photoresist layer and the seed layer covered by the photoresist layer.

"Therein, the seed layer can be made of Ti/TiW/Au; and the metal layer can be made of Au.

"In the above-described chip structure and the fabrication method thereof, the first through opening can be of a polygonal shape, an elliptical shape, a circular shape or a plum blossom shape.

"Further, the conductive trace can have a widened portion and two elongated portions connecting the widened portion to the conductive pad and the conductive via, respectively, and the at least a first through opening can be formed in the widened portion. Furthermore, at least a second through opening can be formed in the elongated portions. In particular, the at least a second through opening can be formed in the elongated portion between the widened portion and the conductive via or formed in the elongated portion between the widened portion and the conductive pad. The at least a second through opening can be of a polygonal shape, an elliptical shape, a circular shape or a plum blossom shape.

"According to the present invention, a first passivation layer is formed on an active surface of a chip with a plurality of electrode pads, and a plurality of first openings is formed in the first passivation layer so as to expose the electrode pads, respectively; then, a redistribution layer is formed on the first passivation layer so as to electrically connect to the electrode pads, wherein the redistribution layer has a plurality of wiring units each comprising a conductive pad, a conductive via formed in one of the first openings, and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; thereafter, a second passivation layer is formed on the first passivation layer and the redistribution layer, wherein the second passivation layer is filled in the at least a first through opening of the conductive trace of each of the wiring units such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer."

URL and more information on this patent, see: Hsu, Hung-Yuan; Kao, Sui-An. Chip Structure Having Redistribution Layer. U.S. Patent Number 8772922, filed January 12, 2012, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8772922.PN.&OS=PN/8772922RS=PN/8772922

Keywords for this news article include: Electronics, Semiconductor, Siliconware Precision Industries Co. Ltd.

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Source: Electronics Newsweekly


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