The assignee for this patent, patent number 8773964, is The Regents of the
Reporters obtained the following quote from the background information supplied by the inventors: "As the on-chip signal switching speeds exceed multi-gigahertz (GHz) and chip densities cross several millions of transistors, parasitic capacitive coupling between adjacent metal wires and the resistive-capacitance (RC) delay due to metal resistance are becoming significant. Crosstalk induced by capacitive coupling between metal wires may degrade signal quality, achievable data bandwidths, power efficiency and interconnect reliability.
"Although these problems can be alleviated by increasing wire-to-wire spacing and decreasing parallel-run length between adjacent links, both of these solutions increase the routing complexity and the area necessary to route metal wires. Signal shielding using grounded metal wires may provide isolation from crosstalk noise. However, signal shielding can increase the metal routing area by 50%. Regular twisting of interconnect suppresses crosstalk in differential links. Yet, twisting requires vias and additional metal layers. The use of vias can increase wire resistance while additional metal layers complicates routing.
"In addition, the aggregate bandwidth demands of chip-to-chip data communications are growing faster than the number of available I/O pins on chips, pushing the data rates of individual links even higher. Each individual link transmitting in the Gb/s range is typically a differential link which requires two input/output (I/O) pins per chip. Single-ended signaling, which requires only one wire (and hence one pin per chip) per link has also been unsuccessful in the Gb/s range owing to the problems caused by switching noise on the supply rails.
"Accordingly, there is a need to develop an improved technique for routing on-chip wires that does not increase routing complexity, chip area, or increase wire resistance, and decreases signal degradation while permitting closer routing of wires over longer distances. There is also a need to develop improved techniques for minimizing the number of I/O pins used to transmit data between integrated chips and other circuitry."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Embodiments in the detailed description reduce the effects of capacitive coupling between data lines of a data bus on a semiconductor die. As an illustrative example, a single-ended data bus system may be configured to communicate data across an on-chip interconnect utilizing synchronous CDMA based spread spectrum techniques. Utilizing a short spread code to spread the data, data signals propagated along each of the data lines may be encoded to suppress cross-talk interference between the data lines. Transmitting a spread spectrum signal across on-chip interconnects for recovery at the terminus permit integrated chip designers to overcome the effects of capacitive cross-talk between adjacent data bus lines.
"Based upon the principles of spread spectrum communications and synchronous CDMA, a short spreading code, S(t), may be used with multiplication operations in the transmitter and the receiver of a high speed data bus to accomplish the spreading and de-spreading operations. For example, for a data bus having a plurality of data lines, divided into odd-links and even-links, the effects of capacitive coupling may be reduced by only multiplying signals on the odd-links with a spreading code that is orthogonal to those on the even-links.
"The embodiments provided herein provide improved cross-talk immunity between adjacent high speed signal lines by applying synchronous CDMA spread spectrum techniques to each of the high speed signal lines. In some examples, the systems, devices, and methods provide improved cross-talk immunity between even and odd data lines. Other embodiments provide improved cross-talk immunity between nearby and adjacent data lines.
"As a first example, a data bus on an integrated circuit die may include a first data line, the first data line having a first end and a second end, and a second data line substantially adjacent to the first data line, the second data line having a first end and a second end. The data bus may further include a first line driver including a first line driver input configured to receive a first data signal and a first line driver output in communication with the first end of the first data line. The first line driver may be configured to drive the first data signal onto the first data line and a first integrator including an input in communication with the second end of the second data line.
"The first integrator may be configured to receive the first data signal and integrate the first data signal to generate a first received output. The data bus may also include a second line driver including a second line driver input and a second line driver output. The second line driver output may be in communication with the first end of the second data line and a first multiplier including a first input configured to receive a second data signal, a second input configured to receive a spread spectrum code, and an output in communication with the second line driver input. The first multiplier may be configured to modulate the second data signal based on the spread spectrum code to generate a modulated signal. The data bus may also include a second multiplier including an output, a first input coupled to the second end of the second data line, and a second input configured to receive a spreading code. The second multiplier may be configured to de-modulate the modulated signal based on the spreading code to generate a de-modulated signal and a second integrator in communication with the output of the second multiplier, the second integrator configured to integrate the de-modulated signal to generate a second received output.
"As another example, a data bus for transmitting data on an integrated circuit may include a first differential signal line including a first signal line and a second signal line, where each of the first signal line and second signal line includes a first end and a second end, and a first multiplier configured to receive a spreading code and a data bit. The first multiplier may be configured to generate a modulated data bit based upon the data bit and a spreading code. The data bus may also include a differential line driver configured to receive the modulated data bit. The differential line driver has a non-inverting output and an inverting output. The non-inverting output is coupled to the first end of the first signal line and the inverting output is coupled to the first end of the second signal line. The differential line driver generates a non-inverted modulated data bit and an inverted modulated data bit. The data bus may further include a second multiplier and a third multiplier. The second multiplier may include a first input in communication with the second end of the first signal line, a second input configured to receive the spreading code, and an output. The second multiplier is configured to generate a non-inverted data bit at the output based upon the spreading code and the non-inverted modulated data bit. A third multiplier includes a first input in communication with the second end of the second signal line, a second input configured to receive the spreading code, and an output. The third multiplier is configured to generate an inverted data bit at the output based upon the spreading code and the inverted modulated data bit. The data bus may also include a differential integrator including a non-inverting input configured to receive the non-inverted data bit and an inverting input configured to receive the inverted data bit.
"Another example system for transmitting data includes a method including providing a data bus on a integrated chip die, wherein the data bus includes a plurality of adjacent data lines, wherein the plurality of adjacent data lines include a first data line adjacent to a second data line. The method further includes modulating a first data bit on the first data line with a first spread spectrum code to generate a first spread signal. The method further includes modulating a second bit on the second data line with a second spread spectrum code to generate a second spread signal. The method further includes de-modulating the first spread signal with the first spread spectrum code and de-modulating the second spread signal with the second spread spectrum code.
"Still another example is a data bus on a semiconductor die that includes one or more data links on the semiconductor die, wherein each of the one or more data links is configured to receive a data bit. Each of the one or more data links has a unique spreading code. Each of the data links includes a first multiplier including a first input configured to receive a data bit signal and a second input configured to receive the unique spreading code, the first multiplier configured to generate a modulated data bit based upon the data bit signal and the unique spreading code of the respective data line. Each of the data links further includes a line driver including a line driver input configured to receive the modulated data bit and a line driver output coupled to a first end of a data line. Each of the data links further includes a second multiplier including a first input coupled to a second end of the data line, a second input configured to receive the unique spreading code, the second multiplier configured to generate a demodulated data bit based upon the modulated data bit and the unique spreading code of the respective data line. Each of the data links also includes an integrator in communication with the second multiplier and is configured to generate an integrated output based upon the demodulated data bit.
"Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings."
For more information, see this patent: Hsueh, Tzu-Chien; Pamarti, Sudhakar. CDMA-Based Crosstalk Cancellation for On-Chip Global High-Speed Links. U.S. Patent Number 8773964, filed
Keywords for this news article include: Electronics, Semiconductor, Capacitive Coupling, The Regents of the
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