The patent's inventors are Kosic, Stephen R. (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Electronic components are subject to operating characteristic variations. Although devices may be manufactured according to specification, no manufacturing technique can guarantee uniformity across all devices. In metal oxide semiconductor (MOS) devices, this variation is often manifested as a shifting of a threshold voltage level. For example, in a comparator circuit, mismatches in the differential pair and mismatches in the current sources may result in a comparator offset, which is a voltage offset that limits the accuracy of the comparator by affecting the performance of a comparison between an input voltage and a reference voltage. Comparator offsets occur not only as a result of random device mismatches, but are also a function of device size. One known method of reducing offsets is to increase device size. However, this requires increased power to maintain gain-bandwidth and regeneration time. For small, low-power comparators, increasing device size may not be a practical option, so that an offset compensation or cancellation scheme is required.
"Comparator offsets may be categorized into two types. A first type, known as DC offset (also referred to herein as a 'static' offset) is a more or less constant offset that exists when the comparator circuit is operational. A second type, referred to herein as a 'dynamic' offset, occurs when the comparator circuit is switched to output a comparator decision based on the values of the inputs to the circuit. Dynamic offsets may be caused by imbalances in the circuit, such as parasitic capacitances that affect circuit components. Therefore, the causes of dynamic offsets may be unrelated to the causes of static offsets.
"Techniques exist to compensate for static offsets. However, dynamic offsets remain a problem."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Example embodiments of the present invention relate to methods and corresponding devices for calibrating comparators in a pipelined analog-to-digital convertor (ADC).
"According to an example embodiment, a first resistor ladder and a second resistor ladder are connected to respective inputs of differential comparators in at least one stage of the ADC pipeline. Each comparator may be provided with its own first and second resistor ladders, the initial tap points of which are selected to form a pair of initial complementary inputs to the comparator. During ADC operation (when the ADC is performing a conversion), a digital residue generated by the at least one stage is calculated using output from subsequent stages, after time aligning the output from the subsequent stages to take into account time differences among the stages. Each residue value is compared to at least one threshold, preferably to an upper threshold as well as a lower threshold. Based on the comparison, the initial tap voltages applied to at least one comparator in the at least one stage may be calibrated by moving to a different tap location in the first and second resistor ladders. The calibration process described above may be repeated, e.g., once per clock cycle for a specified number of cycles, while the ADC is actively performing conversions to correct for offsets in the various comparators of the ADC. Optionally, the calibration process may be repeated as long as the ADC is actively converting input."
For the URL and additional information on this patent, see: Kosic, Stephen R.;
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