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Patent Application Titled "Wafer Supporting Structure, Intermediate Structure of a Semiconductor Package Including the Wafer Supporting Structure"...

July 23, 2014



Patent Application Titled "Wafer Supporting Structure, Intermediate Structure of a Semiconductor Package Including the Wafer Supporting Structure" Published Online

By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors HAN, Jun-Won (Seoul, KR); KIM, Jae-Hyun (Yongin-si, KR); KIM, Tae-Hoon (Anyang-si, KR); LEE, Ho-Geun (Namyangju-si, KR); JEONG, You-Jeong (Seoul, KR); CHOI, Jung-Sik (Seongnam-si, KR), filed on January 3, 2014, was made available online on July 10, 2014.

No assignee for this patent application has been made.

Reporters obtained the following quote from the background information supplied by the inventors: "Example embodiments relate to a wafer supporting structure, an intermediate structure of a semiconductor package including the wafer supporting structure, and a method of manufacturing the semiconductor package using the intermediate structure. More particularly, example embodiments relate to a wafer supporting structure used in stacking wafers, an intermediate structure of a semiconductor package including the wafer supporting structure, and a method of manufacturing the semiconductor package using the intermediate structure.

"Generally, various semiconductor fabrication processes may be formed on a wafer to a plurality of semiconductor chips. In order to mount the semiconductor chips on a printed circuit board (PCB), a packaging process may be performed on the semiconductor chip to form a semiconductor package.

"In order to increase storage capacity of the semiconductor package, technologies for stacking the semiconductor packages may be widely developed. The stacked semiconductor packages may be electrically connected with each other through a plug formed in the semiconductor chip. Further, in order to reduce a thickness of the semiconductor package, a lower surface of the wafer may be partially removed to expose the plug."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "Embodiments may be directed to a wafer supporting structure including a supporting substrate for supporting a wafer, a release layer for detaching the wafer from the supporting substrate, and an adhesive layer for attaching the wafer to the supporting substrate.

"The release layer may be between the supporting substrate and the adhesive layer.

"The adhesive layer may be between the supporting substrate and the release layer.

"Embodiments may also be directed to an intermediate structure of a semiconductor package including a wafer including a plurality of semiconductor chips and conductive bumps electrically connected with the semiconductor chips, a first adhesive layer on the wafer, a supporting substrate that supports the wafer, a release layer to detach the wafer from the supporting substrate, and a second adhesive layer attached to the first adhesive layer.

"The release layer may be between the supporting substrate and the second adhesive layer.

"The release layer may be between the first adhesive layer and the second adhesive layer.

"A sum of thicknesses of the first adhesive layer and the second adhesive layer may be greater than a thickness of the conductive bumps.

"The first adhesive layer and the second adhesive layer may be configured to fully fill spaces between the conductive bumps.

"The wafer may further include plugs built into the wafer and electrically connected to the conductive bumps.

"Embodiments may also be directed to a method of manufacturing a semiconductor package including forming a first adhesive layer on a wafer, the wafer including a plurality of first semiconductor chips, first conductive bumps electrically connected with the first semiconductor chips, and plugs electrically connected to the first conductive bumps, forming a release layer and a second adhesive layer on a supporting substrate, attaching the wafer to the supporting substrate using the first adhesive layer and the second adhesive layer, attaching second semiconductor chips to the wafer to electrically connect the plugs of the first semiconductor chips with second conductive bumps of the second semiconductor chips, and detaching the supporting substrate from the wafer along the release layer.

"Forming the release layer and the second adhesive layer may include forming the release layer on the supporting substrate, and forming the second adhesive layer on the release layer.

"Forming the release layer and the second adhesive layer may include forming the second adhesive layer on the supporting substrate, and forming the release layer on the second adhesive layer.

"The method may further include soft-baking the first adhesive layer to anneal the first adhesive layer.

"The method may further include soft-baking the release layer to anneal the release layer.

"The method may further include soft-baking the second adhesive layer to anneal the second adhesive layer.

"Attaching the second semiconductor chips to the wafer may include hard-baking the first and second adhesive layers to anneal the first and second adhesive layers.

"The method may further include removing a portion of the wafer to expose the plugs.

"Detaching the supporting substrate from the wafer may include fixing edge portions of the wafer, and applying a physical force to the supporting substrate. The physical force may be applied in a vertical direction with respect to the supporting substrate.

"The method may further include removing remaining portions of the first and second adhesive layers on the wafer.

"The remaining portions of the first and second adhesive layers may be removed using a hydrocarbon-containing solution.

"Embodiments may also be directed to a method of manufacturing a semiconductor package including forming a first adhesive layer on a wafer, the wafer including a plurality of first semiconductor chips, first conductive bumps electrically connected with the first semiconductor chips, and plugs electrically connected to the first conductive bumps, soft-baking the first adhesive layer to anneal the first adhesive layer, forming a release layer and a second adhesive layer on a supporting substrate, soft-baking the release layer and the second adhesive layer to anneal the release layer and the second adhesive layer, attaching the wafer to the supporting substrate using the first adhesive layer and the second adhesive layer, hard-baking the first and second adhesive layers to anneal the first and second adhesive layers, attaching second semiconductor chips to the wafer to electrically connect the plugs with second conductive bumps of the second semiconductor chips, and detaching the supporting substrate from the wafer along the release layer.

"Forming the release layer and the second adhesive layer may include forming the release layer on the supporting substrate, and forming the second adhesive layer on the release layer.

"Forming the release layer and the second adhesive layer may include forming the second adhesive layer on the supporting substrate, and forming the release layer on the second adhesive layer.

"The method may include removing a portion of the wafer to expose the plugs.

"Detaching the supporting substrate from the wafer may include fixing edge portions of the wafer, and applying a physical force to the supporting substrate.

"The physical force may be applied in a vertical direction with respect to the supporting substrate.

"The method may further include removing remaining portions of the first and second adhesive layers on the wafer.

"Embodiments may also be directed to an intermediate structure of a semiconductor package including a wafer including conductive bumps on one surface thereof, a first adhesive layer directly on the wafer and conformally covering the conductive bumps, a release layer, the release layer having a property of cracking when a physical force is applied to the release layer, a second adhesive layer, and a supporting substrate. One of the second adhesive layer and the release layer may directly contacts the first adhesive layer and fill a space between the conductive bumps to provide a covering structure, and the other of the second adhesive layer and the release layer may directly contact the covering structure and directly contacts the supporting substrate.

"The second adhesive layer may directly contact the first adhesive layer and fill a space between the conductive bumps to provide the covering structure. The release layer may directly contact the second adhesive layer and the supporting substrate. A sum of thicknesses of the first adhesive layer and the second adhesive layer may be greater than a thickness in a height direction of the conductive bumps.

"The release layer may directly contact the first adhesive layer and fill a space between the conductive bumps to provide the covering structure. The release layer may directly contact the second adhesive layer and the supporting substrate. A sum of thicknesses of the first adhesive layer and the release layer may be greater than a thickness in a height direction of the conductive bumps.

BRIEF DESCRIPTION OF THE DRAWINGS

"Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

"FIG. 1 illustrates a cross-sectional view depicting a wafer supporting structure in accordance with example embodiments;

"FIG. 2 illustrates a cross-sectional view depicting a wafer supporting structure in accordance with example embodiments;

"FIG. 3 illustrates a cross-sectional view depicting an intermediate structure of a semiconductor package including the wafer supporting structure in FIG. 1;

"FIG. 4 illustrates a cross-sectional view depicting an intermediate structure of a semiconductor package including the wafer supporting structure in FIG. 2;

"FIGS. 5 to 13 illustrate cross-sectional views depicting stages of a method of manufacturing a semiconductor package using the intermediate structure in FIG. 3; and

"FIGS. 14 to 22 illustrate cross-sectional views depicting stages of a method of manufacturing a semiconductor package using the intermediate structure in FIG. 4."

For more information, see this patent application: HAN, Jun-Won; KIM, Jae-Hyun; KIM, Tae-Hoon; LEE, Ho-Geun; JEONG, You-Jeong; CHOI, Jung-Sik. Wafer Supporting Structure, Intermediate Structure of a Semiconductor Package Including the Wafer Supporting Structure. Filed January 3, 2014 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6194&p=124&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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