The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory and a memory system for tuning a clock-based parameter.
"AC parameters relating to a semiconductor memory may be varied by controlling the internal/external environments of the semiconductor memory. Lots of testing and tuning works are required for a memory controller to check and optimize the AC parameters.
"For example, an AC parameter 'tDQSCK' indicates a timing difference between a system clock used in a semiconductor memory and a data strobe signal output from the semiconductor memory when a read operation is performed and indicates the degree of an alignment of the data strobe signal and the system clock. The timing of the data strobe signal is determined based on a delay locked loop clock generated from an internal clock generator that is called a delay locked loop (hereinafter referred to as a 'DLL'). Thus, the timing of the data strobe signal has a different value depending on the environments of a DLL block and the related circuits. The environments may include a process, voltage, and temperature (PVT).
"Accordingly, semiconductor memories mounted on a module have a difference in the parameter 'tDCSCK'.
"When a dynamic random access memory (DRAM) is used as a component in a specific memory system, pieces of information are exchanged on the assumption that a data signal and a data strobe signal are reached within a given specification. Accordingly, when receiving the data signal and the data strobe signal from the DRAM, a memory controller has to secure a margin so that a normal operation is performed irrespective of whether the data signal and the data strobe signal are located at which place of a window.
"As described above, since the parameters may be changed by the environments, it is required to check the AC parameters, especially clock-based parameters, to have proper values and to perform lots of tuning works, called training. However, the training requires many times of information exchanges to be taken."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "Exemplary embodiments of the present invention are directed to provide a semiconductor memory and a memory system controller in which the interface information may be optimized without an additional training works.
"In accordance with an embodiment of the present invention, a memory system may include a semiconductor memory including a storage unit configured to store clock-based parameter information in response to a test mode signal and to output the stored clock-based parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the clock-based parameter information from the semiconductor memory device.
"In accordance with another embodiment of the present invention, a operation method of a memory controller may include requesting clock-based parameter information to a semiconductor memory, wherein the clock-based parameter information is stored in a test operation for the semiconductor memory, receiving the clock-based parameter information output from the semiconductor memory, and adjusting an interface value for the semiconductor memory based on the clock-based parameter information.
"In accordance with yet another embodiment of the present invention, a semiconductor memory may include a delay locked loop configured to generate a data strobe signal based on a system clock, and a storage unit configured to store a parameter information in a test operation and to output the stored parameter in a normal operation. The parameter information corresponds to a skew between the data strobe signal and the system clock.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
"FIG. 2 is a detailed block diagram illustrating an embodiment of a storage unit shown in FIG. 1.
"FIG. 3 is a detailed block diagram illustrating another embodiment of a storage unit shown in FIG. 1.
"FIG. 4 is a flowchart illustrating an operation method of a memory system in accordance with an embodiment of the present invention.
"FIG. 5 is a block diagram illustrating an information processing system including a memory system in accordance with an embodiment of the present invention."
For more information, see this patent application: BYUN, Hee-Jin; KWEAN, Ki-Chang. Semiconductor Memory, Memory System, and Operation Method Thereof. Filed
Keywords for this news article include: Electronics,
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