News Column

Patent Application Titled "Semiconductor Device and Associated Method for Manufacturing" Published Online

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Ma, Rongyao (Chengdu, CN); Li, Tieshing (San Jose, CA), filed on December 19, 2013, was made available online on July 10, 2014.

The assignee for this patent application is Chengdu Monolithic Power Systems Co., Ltd.

Reporters obtained the following quote from the background information supplied by the inventors: "Semiconductor devices, such as metal oxide semiconductor field effect transistors ('MOSFETs'), junction field effect transistors ('JFETs'), and double diffused metal-oxide semiconductor (DMOS) transistors etc. are widely used in various electronic products. Generally, to protect a gate oxide of such a semiconductor device from being damaged by electro-static discharge ('ESD'), an ESD protection module is coupled between a gate and a source of the semiconductor device. The ESD protection module is configured to provide a conduction path between the source and the gate of the semiconductor device, once a gate to source voltage of the semiconductor device caused by ESD exceeds an ESD threshold voltage, so that a large extra energy due to ESD can be discharged promptly through the conduction path. The ESD protection module is usually desired to be integrated into the semiconductor device that it is intended to protect for reducing the size and manufacturing cost of the semiconductor device.

"FIG. 1A illustrates schematically a cross-sectional view of a typical semiconductor device 10 having a power transistor such as MOSFET 11 and an ESD protection module 12 integrated together. FIG. 1B illustrates a top plan view of the semiconductor device 10. The cross-sectional view in FIG. 1A can be considered as being cut from the cut line AA' in FIG. 1B. As shown in FIG. 1A, the semiconductor device 10 is formed on a substrate 13 having an active area 10.sub.1 and a termination area 10.sub.2 (also referring to FIG. 1B). The MOSFET 11 is formed in the active area 10.sub.1 of the substrate 13 and may comprise a gate region 15, a source region 16 and a drain region, wherein the drain region comprises a portion of the substrate 13 near the bottom surface S of the substrate 13. In FIG. 1A, the gate region 15 is illustrated as a trenched gate region electrically coupled to a gate metal 17 through a trenched gate runner 15.sub.T and a first interlayer via 22.sub.1. The trenched gate runner 15.sub.T has a same structure as the trenched gate region 15 but with wider trench width to facilitate formation of the via 22.sub.1. The electrical connection of the gate region 15 to the trenched gate runner 15.sub.T is illustrated by a dotted line in FIG. 1A. The source region 16 is electrically coupled to a source metal 18 through a second interlayer via 22.sub.2.

"The ESD protection module 12 is formed on a thick isolation layer 21 atop the termination area 10.sub.2 of the substrate 13, wherein the thick isolation layer 21 electrically isolates the ESD protection module 12 from the substrate 13. Typically, the ESD protection module 12 may comprise a group of PN diodes formed by depositing a polysilicon layer 19 atop the thick isolation layer 21, and subsequently doping the polysilicon layer 19 with P type and N type dopants. The ESD protection module 12 (i.e. the group of PN diodes formed by the alternately arranged P type doped regions and N type doped regions) is electrically coupled between the source metal 18 and the gate metal 17 to protect a gate oxide of gate region 15 from being damaged by a large extra energy due to ESD. The source metal 18 and the gate metal 17 can be electrically coupled to the ESD protection module 12 respectively through a third interlayer via 22.sub.3 and a fourth interlayer via 22.sub.4.

"Now referring to FIG. 1B, the gate metal 17 is formed around the source metal 18 and is normally disposed above the termination area 10.sub.2 of the substrate 13. The gate metal 17 has a gate metal pad 17.sub.1 and a gate metal runner 17.sub.2. Turning back to FIG. 1A, an interlayer dielectric (ILD) layer 20 is normally formed between the metal layer (including the gate metal 17 and the source metal 18) and the substrate 13 and the ESD protection module 12 to isolate the gate metal 17 and the source metal 18 from the substrate 13 and the polysilicon layer 19 of the ESD protection module 12. The first interlayer via 22.sub.1, the second interlayer via 22.sub.2, the third interlayer via 22.sub.3 and the fourth interlayer via 22.sub.4 are formed through the ILD layer 20 and filled with conductive material. However, the first interlayer via 22.sub.1 is generally formed only under the gate metal runner 17.sub.2 but not under the gate metal pad 17.sub.1 since the ESD protection module 12 is disposed under the gate metal pad 17.sub.1, which makes it rather difficult to form an interlayer via from the gate metal pad 17.sub.1 through the ILD layer 20, the polysilicon layer 19 and the thick isolation layer 21 to reach the substrate 13. Therefore, the gate metal pad 17.sub.1 can not be electrically coupled to the gate region 15 through structures like the first interlayer via 22.sub.1 and the trenched gate runner 15.sub.T, which adversely affects the electrical conductivity between the gate region 15 and the gate metal 17.

"Moreover, since the ESD protection module 12 (including the polysilicon layer 19 and the thick isolation layer 21) has a great thickness (measured in the direction perpendicular with the bottom surface S of the substrate 13), there exists a large transition step 23 from the top surface of the MOSFET 11 to the top surface of the ESD protection module 12. This large difference in height between the top surface of the MOSFET 11 and the top surface of the ESD protection module 12 renders a problem for forming the interlayer vias 22.sub.1, 22.sub.2, 22.sub.3 and 22.sub.4. It is generally desired to form these interlayer vias in a same step to simplify manufacturing process and save cost. However, for the semiconductor device 10 in FIG. 1A, the third interlayer via 22.sub.3 and the fourth interlayer via 22.sub.4 which are located on a higher position (at top of the transition step 23) can hardly be formed in the same step for forming the first interlayer via 22.sub.1 and the second interlayer via 22.sub.2 which are located on a lower position (at foot of the transition step 23). For example, when the interlayer vias 22.sub.1, 22.sub.2, 22.sub.3 and 22.sub.4 are formed by etching the ILD layer 20 with the shield of a patterned photoresist layer in a same step, patterning of the photoresist layer may be greatly affected by the large transition step 23 under a given focal depth. If the patterns defining the first and the second interlayer vias 22.sub.1 and 22.sub.2 are focused, the patterns defining the third and the fourth interlayer vias 22.sub.3 and 22.sub.4 may be out of focus. Thus, the third and the fourth interlayer vias 22.sub.3 and 22.sub.4 may not be precisely formed as required or even can not be opened, especially when the required critically dimension of the vias is small."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "In accomplishing the above and other objects, there has been provided, in accordance with an embodiment of the present disclosure, a semiconductor device. The semiconductor device comprises: a semiconductor substrate of a first conductivity type and having an active cell area and a termination area; a semiconductor transistor, formed in the active cell area and having a drain region, a gate region, and a source region; a source metal, formed over the active cell area of the substrate and electrically coupled to the source region; a gate metal, formed over the termination area of the substrate and electrically coupled to the gate region, wherein the gate metal is formed around the source metal and is separated from the source metal with a gap; and an ESD protection structure, formed atop the termination area of the semiconductor substrate and disposed substantially between the source metal and the gate metal, wherein the ESD protection structure comprises a first isolation layer and an ESD protection layer, and wherein the first isolation layer is disposed between the ESD protection layer and the substrate to isolate the ESD protection layer from the substrate; and wherein the ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, and wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion.

"There has been further provided, in accordance with an embodiment of the present disclosure, a method for forming a semiconductor device having a semiconductor transistor and an ESD protection structure. The method comprises: providing a semiconductor substrate having a first conductivity type, wherein the substrate has a top surface and includes an active cell area and a termination area that are respectively designated for forming the semiconductor transistor and the ESD protection structure; forming the semiconductor transistor in the active cell area, wherein forming the semiconductor transistor comprises forming a drain region, a gate region and a source region; forming the ESD protection structure atop the top surface of the substrate over the termination area; forming a source metal over the active cell area of the substrate; and forming a gate metal over the termination area of the substrate around the source metal and separated from the source metal with a gap; wherein forming the ESD protection structure comprises: forming a patterned first isolation layer atop the top surface of the substrate over the termination area, wherein the patterned first isolation layer includes a first thin isolation portion, a second thin isolation portion and a thick middle isolation portion between and connecting the first thin isolation layer and the second thin isolation layer; and forming a patterned ESD protection layer atop the patterned first isolation layer so that the patterned first isolation layer and the patterned ESD protection layer in entirety has a first portion, a second portion and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a thickness greater than that of the first portion and the second portion.

"There has been further provided, in accordance with an embodiment of the present disclosure, a method for forming a semiconductor device having an ESD protection structure. The method comprises: providing a semiconductor substrate having a first conductivity type, wherein the substrate has a top surface and includes an active cell area and a termination area that are respectively designated for forming a semiconductor transistor and the ESD protection structure; forming a trenched gate region in the active cell area and forming a trenched gate contact in the termination area; forming a first isolation layer atop the entire top surface of the substrate and patterning the first isolation layer to form a patterned first isolation layer, wherein the patterned first isolation layer includes a first thin isolation portion, a second thin isolation portion and a thick middle isolation portion between and connecting the first thin isolation layer and the second thin isolation layer, and wherein the thick middle isolation portion has a greater thickness than the first thin isolation layer and the second thin isolation layer; forming an ESD polysilicon layer atop the substrate and the patterned first isolation layer; doping the ESD polysilicon layer with dopants of a second conductivity type opposite to the first conductivity type; patterning the ESD polysilicon layer so that a designed patterned portion of the ESD polysilicon layer remains and overlies the patterned first isolation layer, and that the patterned first isolation layer and the patterned ESD polysilicon layer in entirety has a first portion, a second portion and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a thickness greater than that of the first portion and the second portion; and doping the patterned ESD polysilicon layer with dopants of the first conductivity type so that the patterned ESD polysilicon layer includes a plurality of alternately arranged first-conductivity-type doped zones and second-conductivity-type doped zones; and forming a source metal over the active cell area of the substrate, and forming a gate metal over the termination area of the substrate around the source metal and separated from the source metal with a gap; and wherein the patterned first isolation layer and the patterned ESD polysilicon layer are substantially located between the source metal and the gate metal, and wherein the first portion is adjacent to the source metal and the second portion is adjacent to the gate metal.

BRIEF DESCRIPTION OF THE DRAWINGS

"The following detailed description of various embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which the features are not necessarily drawn to scale but rather are drawn as to best illustrate the pertinent features.

"FIG. 1A illustrates a cross-sectional view of a typical semiconductor device 10 having a power transistor and an ESD protection module integrated together.

"FIG. 1B illustrates a top plan view of the semiconductor device 10.

"FIG. 2 illustrates a cross-sectional view of a semiconductor device 100 in accordance with an exemplary embodiment of the present invention.

"FIG. 3 illustrates a top plan view of the semiconductor device 100 in accordance with an exemplary embodiment of the present invention.

"FIG. 4 illustrates a top plan view illustrating a plan arrangement of the ESD protection layer 110 in accordance with an exemplary embodiment of the present invention.

"FIG. 5 illustrates a three-dimensional perspective view of a portion of the semiconductor device 100 of FIG. 3 in accordance with an embodiment of the present invention.

"FIGS. 6A-6H are cross-sectional views illustrating schematically a sequential process of a method for forming a semiconductor device having an ESD protection structure in accordance with an alternative embodiment of the present invention.

"The use of the same reference label in different drawings indicates the same or like components or structures with substantially the same functions for the sake of simplicity."

For more information, see this patent application: Ma, Rongyao; Li, Tieshing. Semiconductor Device and Associated Method for Manufacturing. Filed December 19, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6295&p=126&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Electronics, Semiconductor, Chengdu Monolithic Power Systems Co. Ltd..

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Source: Electronics Newsweekly


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