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Patent Application Titled "Semiconductor Apparatus and Method of Operating the Same" Published Online

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventor LEE, Nam Jae (Cheongju-si Chungcheongbuk-do, KR), filed on March 18, 2013, was made available online on July 10, 2014.

The assignee for this patent application is Sk Hynix Inc.

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention generally relates to a semiconductor device and a method of operating the same, and more particularly, to a semiconductor device in/from which data can be input/output, and a method of operating the semiconductor device.

"A semiconductor device for storing data may include a volatile memory device and a nonvolatile memory device. A flash memory device is representative of a nonvolatile memory device, in which a threshold voltage of a memory cell is changed according to the stored data. For example, in the method of a Single Level Cell (SLC) method of storing data of one bit in one memory cell, the threshold voltage of memory cells are divided into an erase level and a program level according to the stored data. Further, in a Multi Level Cell (MLC) method of storing data of two bits in one memory cell, the threshold voltages of memory cells are divided into an erase level and first to third program levels according to stored data.

"When electrons are injected to a floating gate for a program operation for storing data, a threshold voltage of a memory cell is increased. However, when the electrons injected to the floating gate are discharged, the threshold voltage of the memory cell is decreased. Further, since the electrons injected to the floating gate of the memory cell escape from the floating gate, the threshold voltage of the memory cell may be lowered. When the threshold voltage is lowered, the data stored in the memory cell is changed, and as a result, an error is generated, thereby degrading an electrical characteristic and reliability."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventor's summary information for this patent application: "The present embodiments are provided to generally provide a semiconductor device capable of improving an electrical characteristic and reliability, and a method of operating the semiconductor device.

"An embodiment of the present invention provides a method of operating a semiconductor device, includes performing a program operation on selected memory cells of a memory block; storing the number of times a program/erase operation is performed with the selected memory cells; and reading the stored number of times a program/erase operation is performed before setting a level of a program verification voltage to be used in a program verification operation.

"An embodiment of the present invention provides a method of operating a semiconductor device, including: performing a program operation of selected memory cells of a memory block; setting a level of a program verification voltage according to the number of times a program/erase operation is performed on the selected memory cells; and performing a program verification operation by applying the program verification voltage of the set level to the selected memory cells, in which the level of the program verification voltage is increased in proportion to the number of times a program/erase operation is performed.

"An embodiment of the present invention provides a method of operating a semiconductor device, including: performing an LSB program loop of memory cells; setting an operation condition according to the number of times a program/erase operation is performed on the memory cells; and performing an MSB program loop of the memory cells according to the operation condition, in which intervals of threshold voltage distributions of the memory cells are determined according to the operation condition.

"An embodiment of the present invention provides a semiconductor device, including: a memory array including a plurality of memory blocks; and a peripheral circuit configured to increase a program verification voltage or adjust intervals between threshold voltage distributions of selected memory cells in proportion to the number of times a program/erase operation is performed on the selected memory cells when a program loop of the selected memory cells in the memory block of the memory array is performed.

"According to the embodiments of the present invention, it is possible to improve an electrical characteristic and reliability.

"The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail embodiments thereof with reference to the attached drawings in which:

"FIG. 1 is a block diagram for describing a semiconductor device according to an embodiment of the present invention;

"FIG. 2 is a circuit diagram for describing a memory array illustrated in FIG. 1;

"FIG. 3 is a distribution diagram for describing a variation of threshold voltages according to the number of times a program/erase operation is performed;

"FIGS. 4A and 4B are flowcharts for describing a method of operating a semiconductor device according to an embodiment of the present invention;

"FIGS. 5A and 5C are distribution diagrams for describing a method of operating a semiconductor device according to an embodiment of the present invention;

"FIG. 6 is a distribution diagram for describing a method of operating a semiconductor device according to an embodiment of the present invention;

"FIG. 7 is a block diagram schematically illustrating a memory system according to an embodiment of the present invention;

"FIG. 8 is a block diagram schematically illustrating a fusion memory device or a fusion memory system for performing a program operation according to the aforementioned various embodiments; and

"FIG. 9 is a block diagram schematically illustrating a computing system including a flash memory device according to an embodiment of the present invention."

For more information, see this patent application: LEE, Nam Jae. Semiconductor Apparatus and Method of Operating the Same. Filed March 18, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4541&p=91&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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