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Patent Application Titled "Field Effect Transistor with Channel Core Modified for a Backgate Bias and Method of Fabrication" Published Online

July 23, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors HIRAI, Tomohiro (Kawasaki-shi, JP); NAGUMO, Toshiharu (Kawasaki-shi, JP), filed on December 19, 2013, was made available online on July 10, 2014.

The assignee for this patent application is Renesas Electronics Corporation.

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to a NanoWire Field Effect Transistor (NWFET) or a finFET in which a channel core is modified to incorporate a feature for controlling threshold voltage. More specifically, the core of the nanowire channel of the NWFET or the core of the fin of the finFET is filled with an electrode material to which can be applied a backbias voltage.

"A recent trend in integrated circuit (IC) design is the use of nanowire transistors. FIG. 1 shows exemplarily a conventional nanowire field effect transistor (NWFET) configuration 100, wherein the nanowire 101 serves as the channel interconnecting the source 102 and drain 103. The gate 104 serves to control conductivity of the channel nanowire 101.

"As shown in FIG. 1A, a gate-all-around nanowire FET 110 has a gate structure 111 that encircles the nanowire 101, as then further covered by a doped polysilicon structure 112. An example of a gate-all-around nanowire FET is described in U.S. Pat. No. 8,173,993 to Bangsaruntip, et al., the contents of which is incorporated herein by reference.

"FIG. 2 shows exemplarily a conventional finFET 200, wherein the fin 201 serves as the channel interconnecting the source 202 and drain 203, with gate 204 serving to control the channel conductivity. Unlike the fin of the finFET, the nanowire channel of the NWFET 100 is typically roughly circular in cross-sectional view and is typically supported to be above the substrate, as exemplarily shown in FIG. 1A.

"To optimize chip performance and leakage, multi-Vt technology is used, wherein different devices have different Ion/Ioff due to their different Vts.

"However, particularly with the miniaturization of electronic devices, as exemplified by the use of NWFETs and finFETs and using conventional fabrication methods, it is difficult to achieve multiple Vt's for NWFETs and finFETs without increasing transistor variability.

"That is, as exemplarily shown in FIG. 3, the conventional planar device receives an impurity implant in a planar manner so as to achieve a uniform impurities profile 301. In contrast, in a nanowire/finFET device 310, the implantation of a channel region 311 is non-planar, so that the non-uniform impurities profile can result in transistor variability 312 at the region surrounded by the gate dielectric layer and the gate layer (G)."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "In view of the foregoing and other exemplary problems, drawbacks, and disadvantages of the conventional methods and systems, an exemplary feature of the present invention is to provide a structure and method of fabrication of NWFETs and finFETs having a feature that the core of the NWFET or finFET has an electrode configured for application of a backbias voltage, thereby providing a mechanism by which threshold voltage can be controlled.

"In a first exemplary aspect of the present invention, described herein is semiconductor device, including a substrate; a source structure and a drain structure formed on the substrate; at least one nanowire structure interconnecting the source structure and drain structure and serving as a channel therebetween; and a gate structure formed over the at least one nanowire structure, to provide a control of a conductivity of carriers in the channel, and the nanowire structure includes a center core serving as a backbias electrode for the channel.

"In a second exemplary aspect, also described herein is a semiconductor device, including a substrate; a source structure and a drain structure formed on the substrate; at least one interconnect structure interconnecting the source structure and the drain structure and serving as a channel therebetween; and a gate structure formed over the at least one interconnect structure to provide a control of a conductivity of carriers in the channel, wherein each of the at least one interconnect structure includes a center core serving as a backbias electrode for the channel.

"In a third exemplary aspect, also described herein is a method of fabricating a semiconductor device, the method including forming a source structure and a drain structure on a substrate; forming at least one interconnect structure interconnecting the source structure and the drain structure, the at least one interconnect structure serving as a channel therebetween; and forming a gate structure over the at least one interconnect structure to provide a control of a conductivity of carriers in the channel, wherein each of the at least one interconnect structure includes a center core serving as a backbias electrode for the channel.

"Other aspects, features and advantages of the invention will be more fully apparent from the ensuing disclosure and appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

"The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which:

"FIG. 1 exemplarily shows a conventional NWFET 100;

"FIG. 1A exemplarily shows a conventional NWFET with gate structure 111 encircling the nanowire 101 to provide a gate-all-around configuration 110;

"FIG. 2 exemplarily shows a conventional finFET 200;

"FIG. 3 illustrates the non-uniform implant characteristics 311 of nanowire/finFETs 310, compared with the uniform implant characteristics 301 of planar devices 300;

"FIG. 4 illustrates a cross-sectional view 400 of a nanowire structure 401 and fin structure 402 of exemplary embodiments of the present invention, demonstrating the backbias electrode core 403;

"FIG. 5 provides an exemplary characteristic curve 400 that demonstrates the effects of the electrode core 403 provided by the present invention;

"FIG. 6 illustrates an initial nanowire formation stage 600 of an exemplary embodiment of the present invention;

"FIG. 7 illustrates a fabrication stage 700 in which the nanowire structures 603 are etched into a substantially circular-cross-section shape;

"FIG. 8 illustrates a fabrication stage 800 in which a silicon layer 801 is deposited on a nanowire 601 and the source/drain regions;

"FIG. 9 illustrates a fabrication stage 900 in which portions of the source/drain regions 801 are etched to form openings 901 to the underlying SiGe layer so that the nanowire cores can be etched out;

"FIGS. 10A-10D illustrates in top and cross sectional views the fabrication stage 1000 in which the SiGe core in the nanowire structure is to be etched out by a wet etching process, from the two ends of the nanowire structure, given that the SiGe material can be selectively etched faster than the Si material;

"FIGS. 11A-11D show top and cross sectional views after the electrode material deposition;

"FIGS. 12A-12D show top and cross sectional views for a fabrication stage 1200 in which the source/drain portions are exposed by polishing;

"FIGS. 13A-13D show top and cross sectional views for a fabrication step in which the gate structure is added using conventional MOS techniques; and

"FIGS. 14A-14D show top and cross sectional view for the final fabrication stage 1400 including contacts for the source/drain and backbias electrode."

For more information, see this patent application: HIRAI, Tomohiro; NAGUMO, Toshiharu. Field Effect Transistor with Channel Core Modified for a Backgate Bias and Method of Fabrication. Filed December 19, 2013 and posted July 10, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6470&p=130&f=G&l=50&d=PG01&S1=20140703.PD.&OS=PD/20140703&RS=PD/20140703

Keywords for this news article include: Semiconductor, Renesas Electronics Corporation.

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Source: Electronics Newsweekly


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