News Column

"Substrate Having a Low Coefficient of Thermal Expansion (Cte) Copper Composite Material" in Patent Application Approval Process

June 12, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventors Rouhana, Layal L. (San Diego, CA); W., Jomaa Houssam (San Diego, CA); Bchir, Omar J. (San Diego, CA), filed on December 14, 2012, was made available online on May 29, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Qualcomm Incorporated.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Various features relate to a substrate having a low coefficient of thermal expansion (CTE) copper composite material.

"There is an ongoing demand to shrink the size of semiconductor device packages. One way to achieve this is to reduce the thickness of the substrate of an integrated circuit, or other integrated circuit components in a device. A substrate is typically made of a central core layer and multiple dielectric layers on either side of the central core layer. Copper or other conductive material is used on the surface of the core and dielectric layers to route signals from the active component of the integrated circuit to the motherboard and other components in a device. The core layer includes a cured dielectric layer with metal (e.g., copper) foil bonded on both sides of the cured dielectric layer (e.g., glass, resin). The buildup dielectric layer is often referred to as a prepreg (pre-impregnated) layer or buildup epoxy and may be laminated or pressed on top of the core during manufacturing. The manufacturing process may or may not use copper foil during the lamination process. In addition, the substrate may also include vias that are made of copper.

"Thinning the substrate of an integrated circuit reduces the stiffness of the composite structure and leads to warpage during chip and/or board mount as well as increasing the overall coplanarity of the package, which can lead to surface mount yield issues. These high temperature warpage and coplanarity problems are related to material properties including the coefficient of thermal expansion (CTE) of the materials comprising the substrate. To eliminate, reduce or minimize these warpage and coplanarity problems, the effective CTE of the substrate needs to be reduced. One approach to reduce the CTE of the substrate is to use very low CTE materials for the dielectric layers (e.g., prepreg or epoxy buildup and core layers). Current available materials in the market for organic substrates can reach down as low as 1-3 parts-per-million per degree Celsius (ppm/.degree. C.). However, the use of these ultra-low CTE materials may be insufficient to offset the high CTE of copper (17 ppm/.degree. C.), especially as the overall substrate thickness is reduced.

"In order to enable the growing need of thinning packages for mobile and other devices, additional reduction in the conductor material CTE is needed to enable substrates that meet warpage and coplanarity requirements during chip mount and surface mount."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "Various features, apparatus and methods described herein provide a substrate for an integrated circuit (IC).

"A first example provides a substrate that includes a first dielectric layer, a second dielectric layer, a core layer, and a composite conductive material. The first and second dielectric layers have a first coefficient of thermal expansion (CTE). The core layer is between the first dielectric layer and the second dielectric layer. The composite conductive trace may be on the first dielectric layer, between the first dielectric layer and the core layer. The composite trace may be between the core layer and the second dielectric layer. The composite trace may be on the second dielectric layer. The composite conductive trace includes copper and another material. The composite conductive trace has a second CTE that is less than a third CTE for copper to more closely match the first CTE for the first and second dielectric layers.

"According to one aspect, the another material is carbon nanotubes (CNTs). In some implementations, the CNTs may include nanotubes coated with a mixed shell of zwitterrionic and a positively charged conductive polymer. In some implementations, the CNTs may include nanotubes coated with a mixed shell of zwitterrionic and a non-conductive polymer.

"According to another aspect, the another material has a fourth CTE value that is negative. The another material may be a nickel/tin alloy in some implementations. The substrate may be for an integrated circuit (IC). The substrate may be for a printed circuit board (PCB) in some implementations. In some implementations, the composite conductive trace is located between the core layer and the first dielectric layer.

"A second example provides a method for manufacturing a substrate. The method provides a core layer for the substrate. The method also provides a composite conductive trace. The composite conductive trace includes copper and another material. The composite conductive trace has a first coefficient of thermal expansion (CTE) that is less than a second CTE for copper to more closely match a third CTE for a first and second dielectric layers, and the core. The method provides the first and second dielectric layers, such that the core layer is between the first and second dielectric layers.

"According to one aspect, providing the composite conductive trace includes paste printing a copper composite layer on at least one of the core layer, first dielectric layer and/or second dielectric layer. In some implementations, the copper composite layer is a copper composite foil. In some implementations, providing the composite conductive trace includes electrolytically plating a copper composite layer on at least the core layer. In some implementations, providing the composite conductive trace includes electrolytically plating a copper composite layer on at least the first dielectric layer.

"According to another aspect, providing the composite conductive trace includes drilling the core layer to provide a trace pattern on the core layer and filling the trace pattern with a copper composite paste to provide the composite conductive trace. In some implementations, providing the composite conductive trace further includes etching a copper foil layer on the core layer before drilling the core layer.

"According to yet another aspect, providing the composite conductive trace includes filling a trace pattern with a copper composite paste. The trace pattern is in at least one of the core layer, first dielectric layer and/or second dielectric layer.

"According to an aspect, providing the composite conductive trace includes applying a dry film resist (DFR) on a first copper layer of the core layer, patterning the DFR, electrolytically plate a second copper composite layer through the DFR, removing the DFR, and selectively etching the first copper layer of the particular dielectric layer to provide the composite conductive trace. In some implementations, providing the composite conductive trace further includes drilling at least one via pattern in the core layer before applying the DFR on the first copper layer of the core layer. In some implementations, the first copper layer is a copper foil having at thickness of 5 microns (.mu.m) or less. In some implementations, providing the composite conductive trace further includes thinning the first copper layer before applying the DFR on the first copper layer of the core layer. The first copper layer is a copper foil having a thickness of 12 microns (.mu.m) or less before the thinning.

"According to another aspect, providing the composite conductive trace includes providing a first copper layer and a primer layer on the core layer. The primer layer is located between the first copper layer and the core layer. In some implementations, providing the composite conductive trace also includes etching the first copper layer, the etching leaving the primer layer on the core layer, electroless plating a second copper layer on top of the layer of primer, applying a dry film resist (DFR) on top of the second copper composite layer, patterning the DFR, electrolytically plate a third copper composite layer through the DFR, removing the DFR, and selectively etching the second copper composite layer of the core layer to provide the composite conductive trace.

DRAWINGS

"Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

"FIG. 1 illustrates a substrate that includes low coefficient of thermal expansion copper composite materials.

"FIG. 2 illustrates a flow diagram for manufacturing a substrate with low coefficient of thermal expansion copper composite materials.

"FIGS. 3A-3D illustrate a shortened sequence of a paste process for manufacturing a substrate with low coefficient of thermal expansion copper composite materials.

"FIGS. 4A-4D illustrate a shortened sequence of a plating process for manufacturing a substrate with low coefficient of thermal expansion copper composite materials.

"FIG. 5 illustrates a flow diagram of a modified semi-additive processing (mSAP) patterning process for manufacturing a substrate with low coefficient of thermal expansion copper composite materials.

"FIG. 6 illustrates a sequence of a mSAP patterning process on a layer of a substrate.

"FIG. 7 illustrates a flow diagram of a semi-additive processing (SAP) patterning process for manufacturing a substrate with low coefficient of thermal expansion copper composite materials.

"FIG. 8 illustrates a sequence of a SAP patterning process on a layer of a substrate.

"FIG. 9 illustrates a flow diagram of a conceptual plating process.

"FIG. 10 illustrates a flow diagram of a conceptual paste process.

"FIG. 11 illustrates various electronic devices that may integrate an integrated circuit and/or PCB described herein."

URL and more information on this patent application, see: Rouhana, Layal L.; W., Jomaa Houssam; Bchir, Omar J. Substrate Having a Low Coefficient of Thermal Expansion (Cte) Copper Composite Material. Filed December 14, 2012 and posted May 29, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5795&p=116&f=G&l=50&d=PG01&S1=20140522.PD.&OS=PD/20140522&RS=PD/20140522

Keywords for this news article include: Nanotube, Nanotechnology, Emerging Technologies, Qualcomm Incorporated.

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Source: Politics & Government Week


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